IEEE International Symposium on Quality Electronic Design最新文献_第8页

Quality of SoC Designs through Quality of the Design Flow: Status and Needs 从设计流程的质量看SoC设计的质量:现状与需求

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10030

P. Magarshack

引用次数: 0

Accurate Estimation of Circuit Delay Variance with Limited Monte Carlo Simulations Using Bayesian Inference 基于贝叶斯推理的有限蒙特卡罗模拟电路延迟方差的精确估计

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED57927.2023.10129384

P. Chithira

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引用次数: 0

Embedded Test Leads to Embedded Quality 嵌入式测试导致嵌入式质量

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10022

Vinod Agrawal

引用次数: 0

0.13 micron: Will the Speed Bumps Slow the Race to Market? 0.13微米:减速带会减缓市场竞争吗?

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10018

B. Alexander, J. Benkoski

{"title":"0.13 micron: Will the Speed Bumps Slow the Race to Market?","authors":"B. Alexander, J. Benkoski","doi":"10.1109/ISQED.2001.10018","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10018","url":null,"abstract":"Description Engineering departments face spiraling expectations to deliver more sophisticated products in less time while coping with the challenges of cutting-edge 0.13 micron technology. Are the tools and methods ready and available to allow the shift to 0.13? Are designers prepared and armed to make 0.13 a mainstream production technology in an economical way within the next 24 months? In the past the next process technologies were brought up to volume production by shrinking existing circuit designs to the new technology. Will this approach work or is it necessary develop all circuits new for 0.13 micron? In 0.13 micron technologies designers, CAD developers and manufacturers are faced with effects like following: Digital designs are beginning to behave like analog circuits. Physical phenomenon, which were not important before, need to be taken into consideration. Timing and noise are becoming intertwined. Design rules are more complex and don’t shrink linearly. New optical effects for masks, yield issues, etc., etc. As the traditional methods are not working any more to shift existing designs to 0.13 micron technology the provocative question comes up; what are the “show stoppers” and what does it take to “let the show go on”? A panel representing system and IC designer, EDA vendors, and semiconductor manufacturing executives will share their experiences, methods, and tools that they use or provide to tackle the 0.13 micron challenges and to accelerate design productivity.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125230941","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Interconnect Modeling for Timing, Signal Integrity and Reliability 互连建模的时序，信号完整性和可靠性

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10040

N. Arora, N. Nagaraj

引用次数: 0

Nanoelectronics: Evolution or Revolution? 纳米电子学:进化还是革命?

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2005.83

Mark S. Lundstrom, Philip Wong, K. Yano

{"title":"Nanoelectronics: Evolution or Revolution?","authors":"Mark S. Lundstrom, Philip Wong, K. Yano","doi":"10.1109/ISQED.2005.83","DOIUrl":"https://doi.org/10.1109/ISQED.2005.83","url":null,"abstract":"Scaling of CMOS technology continues in spite of tremendous technology development barriers, design challenges and prohibitive costs. Today, the 65nm CMOS technology node is moving from development to high volume manufacturing while research and development continues on future technology nodes including 45nm, 30nm and beyond. Design of ICs in these scaled technologies faces new limitations. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. These requirements pose several difficulties across a range of disciplines spanning technology, fabrication, transistor structure, circuits, systems, design, and architecture. On the technology front, the question arises whether we can continue to scale CMOS technology and whether we are close to the end of the ITRS roadmap. Are there any fundamental barriers? Should we continue along the traditional CMOS scaling path reduce effective oxide thickness, improve channel mobility, and minimize parasitic or consider a more radical departure from planar CMOS to non-planar device structures such as tri-gate and FinFET thin body transistors? Will we ever use nanowires and other novel nano devices such as Carbon nanotubes and self-assembled molecular devices? How important is self-assembly and bottom-up manufacturing in making future systems? What options do we have post non-planar CMOS and before more exotic spintronics and quantum devices? On the design front, while researchers are addressing various circuit design techniques to deal with process variation and leakage, it is unclear whether we can build systems with non-planar CMOS devices and other novel nano devices. Do we need new circuit design methods? How do we put systems together either with aggressively scaled Si devices, non-planar CMOS or with self-assembled molecular devices? What are the implications for design community? Will the information processing paradigm shift? Will we learn anything from researching futuristic nanoscale devices, circuits and systems that may impact scaling of Silicon CMOS technology?","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133016996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

nVHDL: A Hardware Design Language for Modeling Discrete and Analog Design and Simulation of Mixed-Signal Electronic Systems (Tutorial Abstract) nVHDL:一种用于混合信号电子系统离散和模拟建模和仿真的硬件设计语言(教程摘要)

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10010

Sumit Ghosh

{"title":"nVHDL: A Hardware Design Language for Modeling Discrete and Analog Design and Simulation of Mixed-Signal Electronic Systems (Tutorial Abstract)","authors":"Sumit Ghosh","doi":"10.1109/ISQED.2002.10010","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10010","url":null,"abstract":"The tutorial will focus on the fundamental principles and concepts that underlie every hardware description language invented to-date. It will begin with a quick survey of the classical HDLs for digital systems, discuss Verilog, and then focus heavily on VHDL. HDLs for analog systems such as VHDL-AMS and their basic weaknesses, starting from the fundamental requirements of mixed-signal electronic designs will be examined. Next, the tutorial will concentrate, through meaningful and real-world examples, on how to accurately model hardware so as to get reliable results from HDL simulations. The issues of concurrent simulation of VHDL models on parallel processors and new transport delay semantics that will enable the modeling of PCI and other sophisticated buses based on electromagnetic reflections will be addressed. Finally, in the tutorial, the present problems with VHDL will be examined and current research in “mixed signal” modeling and simulation, that may constitute the basis for a future evolution in HDL technology, namely nVHDL will be reviewed. Time permitting, the tutorial will also explain how to design HDL simulators.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"94 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125247783","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Achieving Zero ADC Production Test Time with Self-calibration and BIST 通过自校准和BIST实现零ADC生产测试时间

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424333

M. Sarraj, H. Bilhan, W. Mohammed

引用次数: 0

Power/Ground Integrity Issues for Sub-130nm IC Designs (Tutorial Abstract) Sub-130nm IC设计的电源/地完整性问题(教程摘要)

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10005

N. Chang

引用次数: 0

On Synthesizing Memristor-Based Logic Circuits in Area-Constrained Crossbar Arrays 区域约束交叉栅阵列中基于忆阻器的逻辑电路合成研究

IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424249

Hsin-Tsung Lee, Chia-Chun Lin, Yung-Chih Chen, Chun-Yao Wang

引用次数: 0