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Exploiting Programmable Dipole Interaction in Straintronic Nanomagnet Chains for Ising Problems 利用应变电子纳米磁链中可编程偶极相互作用求解问题
IEEE International Symposium on Quality Electronic Design Pub Date : 2023-04-05 DOI: 10.1109/isqed57927.2023.10129331
Nastaran Darabi, Maeesha Binte Hashem, Supriyo Bandyopadhyay, A. Trivedi
{"title":"Exploiting Programmable Dipole Interaction in Straintronic Nanomagnet Chains for Ising Problems","authors":"Nastaran Darabi, Maeesha Binte Hashem, Supriyo Bandyopadhyay, A. Trivedi","doi":"10.1109/isqed57927.2023.10129331","DOIUrl":"https://doi.org/10.1109/isqed57927.2023.10129331","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"164 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116641250","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A2OP: an A* Algorithm OPtimizer with the Heuristic Function for PCB Automatic Routing A2OP:一种具有启发式功能的A*算法优化器
IEEE International Symposium on Quality Electronic Design Pub Date : 2023-04-05 DOI: 10.1109/isqed57927.2023.10129358
Quanbao Guo, Keni Qiu
{"title":"A2OP: an A* Algorithm OPtimizer with the Heuristic Function for PCB Automatic Routing","authors":"Quanbao Guo, Keni Qiu","doi":"10.1109/isqed57927.2023.10129358","DOIUrl":"https://doi.org/10.1109/isqed57927.2023.10129358","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130986454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access 基于非常规h树和中心引脚接入的SRAM应用互连探索
IEEE International Symposium on Quality Electronic Design Pub Date : 2023-04-05 DOI: 10.1109/isqed57927.2023.10129316
Zhenlin Pei, M. Mayahinia, Hsiao-Hsuan Liu, M. Tahoori, S. Salahuddin, F. Catthoor, Z. Tokei, C. Pan
{"title":"Emerging Interconnect Exploration for SRAM Application Using Nonconventional H-Tree and Center-Pin Access","authors":"Zhenlin Pei, M. Mayahinia, Hsiao-Hsuan Liu, M. Tahoori, S. Salahuddin, F. Catthoor, Z. Tokei, C. Pan","doi":"10.1109/isqed57927.2023.10129316","DOIUrl":"https://doi.org/10.1109/isqed57927.2023.10129316","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-05","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125112104","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Bit-Parallel Deterministic Stochastic Multiplier 位并行确定性随机乘法器
IEEE International Symposium on Quality Electronic Design Pub Date : 2023-02-14 DOI: 10.48550/arXiv.2302.08324
Sairam Sri Vatsavai, Ishan G. Thakkar
{"title":"A Bit-Parallel Deterministic Stochastic Multiplier","authors":"Sairam Sri Vatsavai, Ishan G. Thakkar","doi":"10.48550/arXiv.2302.08324","DOIUrl":"https://doi.org/10.48550/arXiv.2302.08324","url":null,"abstract":"This paper presents a novel bit-parallel deterministic stochastic multiplier, which improves the area-energy-latency product by up to 10.6$times$10$^4$, while improving the computational error by 32.2%, compared to three prior stochastic multipliers.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"81 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-02-14","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121688275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quantum Technology for Comparator Circuit 比较器电路的量子技术
IEEE International Symposium on Quality Electronic Design Pub Date : 2022-04-06 DOI: 10.1109/isqed54688.2022.9806275
H. Babu, K. M. Uddin, Rownak Borhan Himel, Nitish Biswas
{"title":"Quantum Technology for Comparator Circuit","authors":"H. Babu, K. M. Uddin, Rownak Borhan Himel, Nitish Biswas","doi":"10.1109/isqed54688.2022.9806275","DOIUrl":"https://doi.org/10.1109/isqed54688.2022.9806275","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123705764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding 基于符号断言和代码分解的离线硬件安全评估方法
IEEE International Symposium on Quality Electronic Design Pub Date : 2022-04-06 DOI: 10.1109/isqed54688.2022.9806234
Z. Kazemi, Amin Norollah, M. Fazeli, D. Hély, V. Beroulle
{"title":"An Offline Hardware Security Assessment Approach using Symbol Assertion and Code Shredding","authors":"Z. Kazemi, Amin Norollah, M. Fazeli, D. Hély, V. Beroulle","doi":"10.1109/isqed54688.2022.9806234","DOIUrl":"https://doi.org/10.1109/isqed54688.2022.9806234","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126342022","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Density Aware Cell Library Design for Design-Technology Co-Optimization 面向设计-技术协同优化的密度感知单元库设计
IEEE International Symposium on Quality Electronic Design Pub Date : 2022-04-06 DOI: 10.1109/isqed54688.2022.9806236
S. Nishizawa, T. Nakura
{"title":"Density Aware Cell Library Design for Design-Technology Co-Optimization","authors":"S. Nishizawa, T. Nakura","doi":"10.1109/isqed54688.2022.9806236","DOIUrl":"https://doi.org/10.1109/isqed54688.2022.9806236","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127698226","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Sub-Space Modeling: An Enrollment Solution for XOR Arbiter PUF using Machine Learning 子空间建模:基于机器学习的XOR仲裁者PUF注册解决方案
IEEE International Symposium on Quality Electronic Design Pub Date : 2022-04-06 DOI: 10.1109/isqed54688.2022.9806267
Amir Ali Pour, D. Hély, V. Beroulle, G. D. Natale
{"title":"Sub-Space Modeling: An Enrollment Solution for XOR Arbiter PUF using Machine Learning","authors":"Amir Ali Pour, D. Hély, V. Beroulle, G. D. Natale","doi":"10.1109/isqed54688.2022.9806267","DOIUrl":"https://doi.org/10.1109/isqed54688.2022.9806267","url":null,"abstract":"—In this work we present sub-space modeling of XOR Arbiter PUF as a cost efficient solution for enrollment for the designers’ community. Our goal is to demonstrate a method which can reduce the overall cost in terms of number of CRPs required for training, training time and memory. Here we propose to reduce the complexity of the modeling target by dividing the PUF into smaller sub-components and model each sub-component of the PUF independently. Our early experimental assessment show that our sub-space modeling can significantly reduce the cost of training compared to some of the latest works, thus it is potentially a cost-efficient solution to enroll strong PUF with high complexity.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132771263","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs 超越Verilog:用微小设计评估凿子与高级合成
IEEE International Symposium on Quality Electronic Design Pub Date : 2022-04-06 DOI: 10.1109/isqed54688.2022.9806141
Xiangdong Wei, Xinfei Guo
{"title":"Beyond Verilog: Evaluating Chisel versus High-level Synthesis with Tiny Designs","authors":"Xiangdong Wei, Xinfei Guo","doi":"10.1109/isqed54688.2022.9806141","DOIUrl":"https://doi.org/10.1109/isqed54688.2022.9806141","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"93 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114872716","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks 研究hls设计的Chaskey-12电路对电源侧信道攻击的脆弱性
IEEE International Symposium on Quality Electronic Design Pub Date : 2022-04-06 DOI: 10.1109/isqed54688.2022.9806252
Saya Inagaki, Mingyu Yang, Yang Li, K. Sakiyama, Yuko Hara-Azumi
{"title":"Examining Vulnerability of HLS-designed Chaskey-12 Circuits to Power Side-Channel Attacks","authors":"Saya Inagaki, Mingyu Yang, Yang Li, K. Sakiyama, Yuko Hara-Azumi","doi":"10.1109/isqed54688.2022.9806252","DOIUrl":"https://doi.org/10.1109/isqed54688.2022.9806252","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2022-04-06","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129227569","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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