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IEEE International Symposium on Quality Electronic Design最新文献

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What You Don't Know CAN Hurt You: Designing for Survival in a Sub-wavelength Environment 你不知道的东西会伤害你:在亚波长环境中为生存而设计
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10018
Y. C. Pati
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引用次数: 0
Enhancing the Silicon-Package Interface Through Their Concurrent Design and Verification 通过并行设计和验证增强硅封装接口
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2003.10014
M. Casale-Rossi
{"title":"Enhancing the Silicon-Package Interface Through Their Concurrent Design and Verification","authors":"M. Casale-Rossi","doi":"10.1109/ISQED.2003.10014","DOIUrl":"https://doi.org/10.1109/ISQED.2003.10014","url":null,"abstract":"Unfortunately most design methodologies result in a segregated relationship between IC and package, making coordinated planning a difficult and time-consuming task. The serial nature of the traditional silicon to package design flow limits the effectiveness of existing tools for concurrent planning. Both IC and package design tools lack the needed visibility into their respective neighboring environments to be of use. This serial approach may lead to a poor IC to package netlist resulting in overly complex custom package designs, increased packaging costs, longer cycle times and less than optimal silicon performance. Although BGA and flip-chip provide a vehicle to interface high performance silicon to the system, a methodology change is needed to realize its full performance potential.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"166 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121233812","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Expanding Use of Formal Techniques in Electronic Design 正式技术在电子设计中的扩展应用
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10007
R. Camposano
{"title":"The Expanding Use of Formal Techniques in Electronic Design","authors":"R. Camposano","doi":"10.1109/ISQED.2001.10007","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10007","url":null,"abstract":"Although Electronic Design Automation (EDA) tools allow some tolerance for features having only limited scope or not working in all cases, there is no tolerance for error in their final results. Since the beginning, EDA tools have included socalled “formal” techniques to ensure such error-free results. More and more, formal verification tools are being adopted as a necessary part of mainstream design flows to tackle the exploding verification challenge. In this keynote address, we will focus on some of these formal techniques; in particular, equivalence checking, property checking, and the combination of simulation with formal techniques — all of which play an important role in creating zero-defect results in state-ofthe-art electronic design.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128490155","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
On-Chip Inductance Extraction and Modeling 片上电感提取与建模
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10019
T. Young
{"title":"On-Chip Inductance Extraction and Modeling","authors":"T. Young","doi":"10.1109/ISQED.2001.10019","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10019","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121439416","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Modeling Intrinsic Fluctuations in Decananometer MOS Modeling Intrinsic Fluctuations in Decananometer MOS Decananometer MOS的固有波动建模
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2005.79
N. Gunther, E. Hamadeh, D. Niemann, I. Pesic, Mahmudur Rahman
{"title":"Modeling Intrinsic Fluctuations in Decananometer MOS Modeling Intrinsic Fluctuations in Decananometer MOS","authors":"N. Gunther, E. Hamadeh, D. Niemann, I. Pesic, Mahmudur Rahman","doi":"10.1109/ISQED.2005.79","DOIUrl":"https://doi.org/10.1109/ISQED.2005.79","url":null,"abstract":"Intra-die random fluctuation outcomes inherent to fabrication processes such as gate LER give rise to corresponding fluctuations in device characteristics. These fluctuations become significant for devices with channel length less than 50 nm, a feature size rapidly approaching practical interest. At this scale, the fringe electric field and the charge confinement near the interface play dominant roles in determining MOS device properties and their fluctuations. In this work, we first characterize LER as a lognormal probability density function (pdf) in spatial frequency. Then we apply a 3D quantum mechanically corrected variational principle (VQM) to obtain closed-form expressions for standard deviation of threshold voltage and device capacitance due to LER. Our approach provides a simple physics based alternative to the presently available TCAD simulation for investigating these complex issues as functions of gate size, oxide thickness, and channel doping level.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125024202","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract) 深亚微米最先进的ESD设计中的问题(教程摘要)
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10013
C. Duvvury
{"title":"Issues in Deep Submicron State-of-the-Art ESD Design (Tutorial Abstract)","authors":"C. Duvvury","doi":"10.1109/ISQED.2002.10013","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10013","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125633925","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
System-on-Chip: Embedded Test Strategies 片上系统:嵌入式测试策略
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10015
Y. Zorian
{"title":"System-on-Chip: Embedded Test Strategies","authors":"Y. Zorian","doi":"10.1109/ISQED.2001.10015","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10015","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124905632","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Quality of Design from an IC Manufacturing Perspective 从集成电路制造的角度看设计质量
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10027
Wojciech Maly
{"title":"Quality of Design from an IC Manufacturing Perspective","authors":"Wojciech Maly","doi":"10.1109/ISQED.2001.10027","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10027","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129670472","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Test Structures for Circuit Yield Assessment and Modeling 电路成品率评估与建模测试结构
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2003.10009
D. Boning
{"title":"Test Structures for Circuit Yield Assessment and Modeling","authors":"D. Boning","doi":"10.1109/ISQED.2003.10009","DOIUrl":"https://doi.org/10.1109/ISQED.2003.10009","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128935396","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved pipeline data flow for DySER-based platform 改进了基于dyser平台的管道数据流
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2015.7085413
Zijian Hou, Xin Chen, W. He
{"title":"Improved pipeline data flow for DySER-based platform","authors":"Zijian Hou, Xin Chen, W. He","doi":"10.1109/ISQED.2015.7085413","DOIUrl":"https://doi.org/10.1109/ISQED.2015.7085413","url":null,"abstract":"The coarse-grained reconfigurable architecture(CGRA) has advantages over the traditional FPGAs in terms of delay, area and configuration time. DySER is a novel architecture of the CGRA, which can support both functionally specialization and parallelism specialization. In this paper, the relationship between the bandwidth, data transmission time and RC array scale of DySER-based platform have been analyzed. To improve the architecture, we also present a new data transmission mode called incomplete three-phase pipeline. Compared with the original platform, the results show that the improved platform increases the whole time efficiency by 11% to 15%.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122599773","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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