Enhancing the Silicon-Package Interface Through Their Concurrent Design and Verification

Unfortunately most design methodologies result in a segregated relationship between IC and package, making coordinated planning a difficult and time-consuming task. The serial nature of the traditional silicon to package design flow limits the effectiveness of existing tools for concurrent planning. Both IC and package design tools lack the needed visibility into their respective neighboring environments to be of use. This serial approach may lead to a poor IC to package netlist resulting in overly complex custom package designs, increased packaging costs, longer cycle times and less than optimal silicon performance. Although BGA and flip-chip provide a vehicle to interface high performance silicon to the system, a methodology change is needed to realize its full performance potential.