{"title":"改进了基于dyser平台的管道数据流","authors":"Zijian Hou, Xin Chen, W. He","doi":"10.1109/ISQED.2015.7085413","DOIUrl":null,"url":null,"abstract":"The coarse-grained reconfigurable architecture(CGRA) has advantages over the traditional FPGAs in terms of delay, area and configuration time. DySER is a novel architecture of the CGRA, which can support both functionally specialization and parallelism specialization. In this paper, the relationship between the bandwidth, data transmission time and RC array scale of DySER-based platform have been analyzed. To improve the architecture, we also present a new data transmission mode called incomplete three-phase pipeline. Compared with the original platform, the results show that the improved platform increases the whole time efficiency by 11% to 15%.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"18 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Improved pipeline data flow for DySER-based platform\",\"authors\":\"Zijian Hou, Xin Chen, W. He\",\"doi\":\"10.1109/ISQED.2015.7085413\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"The coarse-grained reconfigurable architecture(CGRA) has advantages over the traditional FPGAs in terms of delay, area and configuration time. DySER is a novel architecture of the CGRA, which can support both functionally specialization and parallelism specialization. In this paper, the relationship between the bandwidth, data transmission time and RC array scale of DySER-based platform have been analyzed. To improve the architecture, we also present a new data transmission mode called incomplete three-phase pipeline. Compared with the original platform, the results show that the improved platform increases the whole time efficiency by 11% to 15%.\",\"PeriodicalId\":302936,\"journal\":{\"name\":\"IEEE International Symposium on Quality Electronic Design\",\"volume\":\"18 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2015.7085413\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2015.7085413","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Improved pipeline data flow for DySER-based platform
The coarse-grained reconfigurable architecture(CGRA) has advantages over the traditional FPGAs in terms of delay, area and configuration time. DySER is a novel architecture of the CGRA, which can support both functionally specialization and parallelism specialization. In this paper, the relationship between the bandwidth, data transmission time and RC array scale of DySER-based platform have been analyzed. To improve the architecture, we also present a new data transmission mode called incomplete three-phase pipeline. Compared with the original platform, the results show that the improved platform increases the whole time efficiency by 11% to 15%.
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