IEEE International Symposium on Quality Electronic Design最新文献

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Global Multi-voltage Interface Unit for Diverse Digital Logic 用于多种数字逻辑的全局多电压接口单元
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424352
N. Prashanth, M. Girish, Sandeep Motebennur, K. Prasanna, Karthik Suman
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引用次数: 0
A New Foe in GPUs: Power Side-Channel Attacks on Neural Network gpu的新敌人:神经网络的功率侧信道攻击
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424358
Hyeran Jeon, Nima Karimian, T. Lehman
{"title":"A New Foe in GPUs: Power Side-Channel Attacks on Neural Network","authors":"Hyeran Jeon, Nima Karimian, T. Lehman","doi":"10.1109/ISQED51717.2021.9424358","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424358","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121110605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Evening Panel Discussion: Are the Interoperability Standards for EDA Too Little/Too Late for Real SoC Designs? 晚上小组讨论:EDA的互操作性标准对于真正的SoC设计来说是否太小/太晚了?
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10012
P. Chatterjee, R. Goering
{"title":"Evening Panel Discussion: Are the Interoperability Standards for EDA Too Little/Too Late for Real SoC Designs?","authors":"P. Chatterjee, R. Goering","doi":"10.1109/ISQED.2002.10012","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10012","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"95 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128330143","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Why Integrated Yield Management is a Necessity 为什么需要综合产量管理
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10021
Y. Lepejian
{"title":"Why Integrated Yield Management is a Necessity","authors":"Y. Lepejian","doi":"10.1109/ISQED.2002.10021","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10021","url":null,"abstract":"Improving semiconductor yield is a multi-facetted process that must include design, manufacturing, and test. An integrated approach enables companies to rapidly reach higher levels of revenue and profitability. Incorporating design-for-yield concepts early, improving the quality of the test programs, and applying new technology to accelerate the measurement and correction of failure sources in the production process combine to have powerful effect upon company profits, product quality, and time to volume.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131564142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Future Platform for Mobile Communication 未来移动通信平台
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10011
H. Sasaki
{"title":"Future Platform for Mobile Communication","authors":"H. Sasaki","doi":"10.1109/ISQED.2001.10011","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10011","url":null,"abstract":"Chairman of the Board NEC I see three driving forces in the IT revolution that are actualizing an Information Society: first, the Internet global, ever expanding nature and second, mobile ability to create the ultimate personal information tool. And last, at the heart of these forces is the cutting-edge semiconductor device. Especially in mobile where products are composed primarily of semiconductors, we see that the creation of advanced semiconductor devices controls to a large degree the superior nature of the mobile product. Mobile products must balance many constraining criteria such as size and weight against functionality such as low power consumption. There are also a wide array of technologies involved such as low power consumption circuit design, flash memory and RF power device. Additionally, intellectual property has become even more important. Moreover, the harmonization of semiconductor technology and peripheral technologies such as small-scale, light weight packaging technology, long life rechargeable batteries and flat panel displays has become an important factor. This keynote speech will focus on 1) the future of mobile technology and 2) the structural changes occurring in the semiconductor industry. In discussing these two trends, I will address the potential shape of the mobile communication platform of tomorrow. About Hajime Sasaki Mr. Hajime Sasaki was born in 1936. After receiving a master's degree of engineering in the field of electrical engineering from the graduate school of the University of Tokyo in 1961, he joined NEC Corporation. He served as General Manager of the VLSI Development Division and General Manager of the Microcomputer Products Division before being elected to the Board of Directors in 1988. He was appointed Senior Executive Vice President in 1996 in charge of semiconductors operations, and in 1999 elected to his current position of Chairman of the Board. Mr. Sasaki received the commendation from the Minister of State for Science and Technology, as a person of scientific and technological merits in 1995. He is a fellow of IEEE since 1996. In 1999 he became the Chairperson of the Communications Industry Association of Japan. In 2000 he received the Third Millennium Medal from IEEE. Also he was elected as the member of NAE (National Academy of Engineering).","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131369327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
FPGA Accelerated Parameterized Cache Simulator FPGA加速参数化缓存模拟器
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424272
Shivani Shah, Sahithi Meenakshi Vutakuru, Nanditha P. Rao
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引用次数: 0
Confluence of AI/ML with EDA and Software Engineering AI/ML与EDA和软件工程的融合
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424251
A. Venkatachar
{"title":"Confluence of AI/ML with EDA and Software Engineering","authors":"A. Venkatachar","doi":"10.1109/ISQED51717.2021.9424251","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424251","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126590378","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells 用于片上系统I/O单元的反向偏置调制UTBB SOI
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424294
Ming-Yu Chang, Po-Yu Chao, M. Chiang
{"title":"Back-Bias Modulated UTBB SOI for System-on-Chip I/O Cells","authors":"Ming-Yu Chang, Po-Yu Chao, M. Chiang","doi":"10.1109/ISQED51717.2021.9424294","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424294","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114513230","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Plenary Session 2P 全体会议2P
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2005.94
L. Józwiak, Kaustav Banerjee
{"title":"Plenary Session 2P","authors":"L. Józwiak, Kaustav Banerjee","doi":"10.1109/ISQED.2005.94","DOIUrl":"https://doi.org/10.1109/ISQED.2005.94","url":null,"abstract":"This session features exciting keynote speeches by Rajeev Madhavan (Chairman & CEO, Magma Design Automation), Michael Reinhardt (CEO & President, RubiCAD), and Shekhar Borker (Intel Fellow & Director of Circuit Research Lab). In the first keynote speech, titled “Addressing the IC Designer’s Needs: Integrated Design Software for Faster, More Economical Chip Design”, Rajeev Madhaven highlights the EDA industry’s need to deliver integrated design flows that enable the design and production of chips with fewer resources and in less time, and without compromising the quality of results.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122705499","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Evening Panel Discussion: Process Variation: Is It Too Much to Handle? 晚上小组讨论:过程变化:是否太过难以处理?
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10015
Ron Wilson, S. Narendra, V. De
{"title":"Evening Panel Discussion: Process Variation: Is It Too Much to Handle?","authors":"Ron Wilson, S. Narendra, V. De","doi":"10.1109/ISQED.2002.10015","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10015","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129790190","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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