IEEE International Symposium on Quality Electronic Design最新文献_第2页

Challenges of Securing Low-Power LoRaWAN Devices Deployed in Advanced Manufacturing 确保低功耗LoRaWAN设备部署在先进制造中的挑战

IEEE International Symposium on Quality Electronic Design Pub Date : 2022-04-06 DOI: 10.1109/isqed54688.2022.9806290

M. Monjur, Joseph Heacock, Joshua Calzadillas, Rui Sun, Qiaoyan Yu

引用次数: 1

Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations 考虑温度和ITC变化的Si/Ge异质结非对称双栅DLTFET性能研究

IEEE International Symposium on Quality Electronic Design Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424354

Suruchi Sharma, R. Basu, B. Kaur

引用次数: 0

SALAH: Simulation-Assisted LAyout Hierarchy Construction SALAH:模拟辅助布局层次结构

IEEE International Symposium on Quality Electronic Design Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424317

Sherif Hany, E. Hegazi, Hany Fekri Ragaai

引用次数: 0

LEC Vulnerability on Constant Propagation 恒定传播的LEC漏洞

IEEE International Symposium on Quality Electronic Design Pub Date : 2021-04-07 DOI: 10.1109/ISQED51717.2021.9424340

S. Srivastav, Ming Yi Lim, Babu Trp, K. Y. Jeevan

引用次数: 0

Power-aware testing in the Era of IoT 物联网时代的功耗感知测试

IEEE International Symposium on Quality Electronic Design Pub Date : 2018-03-13 DOI: 10.1109/ISQED.2018.8357254

P. Girard

引用次数: 0

A new era of computing: Are you "ready now" to build a smarter and secured enterprise? 计算的新时代:您“现在准备好”构建一个更智能、更安全的企业了吗?

IEEE International Symposium on Quality Electronic Design Pub Date : 2014-03-03 DOI: 10.1109/ISQED.2014.6783293

Jacqueline Woods, S. Iyengar, A. Sinha, S. Mitra, Stacy Cannady

引用次数: 1

New electrical design verification approach for 2.5D/3D package signal and power integrity 2.5D/3D封装信号和电源完整性的新电气设计验证方法

IEEE International Symposium on Quality Electronic Design Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523586

N. Karim

{"title":"New electrical design verification approach for 2.5D/3D package signal and power integrity","authors":"N. Karim","doi":"10.1109/ISQED.2013.6523586","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523586","url":null,"abstract":"A 2.5D/3D multi die interposer with TSV (Through Silicon Via) allows massive wide parallel busses between memory and logics devices, improves speed, and significantly reduces power consumption. The TSV and silicon interposer are amongst the most promising technologies that offer the greatest vertical interconnects density. This new establishment will change the semiconductor industry paradigm for many years to come. 2.5D/3D technology introduces a new degree of electrical design complexity which is unfamiliar to many existing electrical design methodologies and EDA tools. A new electrical verification methodology must be developed with consideration to the micro level (TSV and interposer structures) and macro/system level simulation. At the Micro level, modeling of TSV is challenging due to its dependency on the material properties of the medium surrounding it and its impact on the signal losses/attenuation, capacitance effects, and the coupling among the vertical interconnects. At the Macro level, new electrical characteristics of the system need to be closely coupled with the thermal and mechanical tolerances of the entire 2.5D/3D packaging structure in order for its ultra wideband data exchange between logic chip and memory chips. TSV placement on logic and memory chips must be carefully placed during the chip design placement stage in order to avoid unnecessary electromagnetic coupling and faulty logic latching. Traditional separate signal and power integrity analysis methodologies are no longer sufficient due to the close proximity of the power and signal distribution network. In order to accurately predict the performance of 2.5D/3D packages, a new design paradigm shift is needed to toggle 2.5D/3D system performance optimization. New design and modeling approaches along with new breeds of computational electromagnetic EDA tools, are paramount to predicting the performance of 2.5D/3D packages.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2013-03-04","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122445872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Advances in wire routing 布线技术的进展

IEEE International Symposium on Quality Electronic Design Pub Date : 2013-03-04 DOI: 10.1109/ISQED.2013.6523619

Martin D. F. Wong

引用次数: 0

Modeling and analyzing NBTI in the presence of Process Variation 存在工艺变异的NBTI建模与分析

IEEE International Symposium on Quality Electronic Design Pub Date : 2011-03-14 DOI: 10.1109/ISQED.2011.5770699

Taniya Siddiqua, S. Gurumurthi, M. Stan

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引用次数: 37

Quality Driven Manufacturing and SOC Designs 质量驱动制造和SOC设计

IEEE International Symposium on Quality Electronic Design Pub Date : 2007-03-26 DOI: 10.1109/ISQED.2007.131

S. Venkataraman, Nagesh Nagapalli, L. Józwiak

引用次数: 0