{"title":"恒定传播的LEC漏洞","authors":"S. Srivastav, Ming Yi Lim, Babu Trp, K. Y. Jeevan","doi":"10.1109/ISQED51717.2021.9424340","DOIUrl":null,"url":null,"abstract":"LEC is the most widely used tool for formal equivalence verification and ECO generation, but there are gaps in modeling of constant in LEC which can lead to silicon bugs even though the verification has passed. This issue is observed in designs which have gone through ECO’s. This paper covers scenarios where there are potential bugs masked by LEC/ECO due to this limitation and proposes a methodology to mitigate it.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"12 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"LEC Vulnerability on Constant Propagation\",\"authors\":\"S. Srivastav, Ming Yi Lim, Babu Trp, K. Y. Jeevan\",\"doi\":\"10.1109/ISQED51717.2021.9424340\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"LEC is the most widely used tool for formal equivalence verification and ECO generation, but there are gaps in modeling of constant in LEC which can lead to silicon bugs even though the verification has passed. This issue is observed in designs which have gone through ECO’s. This paper covers scenarios where there are potential bugs masked by LEC/ECO due to this limitation and proposes a methodology to mitigate it.\",\"PeriodicalId\":302936,\"journal\":{\"name\":\"IEEE International Symposium on Quality Electronic Design\",\"volume\":\"12 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-04-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED51717.2021.9424340\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED51717.2021.9424340","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
LEC is the most widely used tool for formal equivalence verification and ECO generation, but there are gaps in modeling of constant in LEC which can lead to silicon bugs even though the verification has passed. This issue is observed in designs which have gone through ECO’s. This paper covers scenarios where there are potential bugs masked by LEC/ECO due to this limitation and proposes a methodology to mitigate it.
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