IEEE International Symposium on Quality Electronic Design最新文献

{"title":"DFM, DFY, Debug and Diagnosis: The Loop to Ensure Yield","authors":"S. Venkataraman","doi":"10.1109/ISQED.2007.61","DOIUrl":"https://doi.org/10.1109/ISQED.2007.61","url":null,"abstract":"Semiconductor yield has traditionally been limited by random particle-defect based issues.However, as the feature sizes reduced to 0.13 micron and below, systematic mechanism-limited yield loss began to appear as a substantial component in yield loss. In addition, it is becoming clear that ramping yield would take longer and final yields would not reach historical norms.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2007-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124757221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Session EP1: Power Management and Optimization Challenges for Sub 90nm CMOS Designs- What is the Real Cost of Long Battery Life?","authors":"M. Santarini, P. Chatterjee","doi":"10.1109/ISQED.2006.114","DOIUrl":"https://doi.org/10.1109/ISQED.2006.114","url":null,"abstract":"The recent migration to DSM process geometries and very large gate counts, has created a need for low power design and multi-voltage designs as standard rather than the exception. The variety of power optimization and power planning tools has resulted in ad-hock modification to existing design flows to accommodate the new requirements. This has given rise to wide variation in the QOR of the silicon that incorporates these design features. The panel will review and discuss places in the design flow where power planning and optimization are beneficial to improving QOR and also some of the analysis and signoff limitations to the automation that is available and directed at this task.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117044764","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Who is really responsible for quality throughout the design process?","authors":"Ron Wilson, D. Overhauser","doi":"10.1109/ISQED.2006.146","DOIUrl":"https://doi.org/10.1109/ISQED.2006.146","url":null,"abstract":"From development through manufacturing an IP core undergoes many different stages that can affect the overall quality and characteristics of the core. When a project is slowed or halted because of a problem with the IP core then who is responsible? Is it the IP provider who provided a core that worked at delivery, the integrator that made changes as necessary or perhaps the manufacturer? This panel will explore the many possible causes of problems with an IP core, but more importantly it will examine what is being done to minimize the risk associated with third party IP and who is responsible.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131482279","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Simplicity and Executability: Cornerstones of Quality","authors":"M. Keating","doi":"10.1109/ISQED.2006.116","DOIUrl":"https://doi.org/10.1109/ISQED.2006.116","url":null,"abstract":"There are two great truths in design: If it's not tested, it's broken. And if it's not simple, it's broken. This talk will focus on aspects of both issues. Code is the natural form of communication between designer and compiler; yet most code is demonstrably not simple; hence it is broken. Drawings are the natural form of communication between engineers, and user documents are how we communicate to customers. Yet typically, these documents are not executable, and thus not tested; hence they are all broken. Similarly, state machines and inter-module interfaces are often many orders of magnitude more complex than needed; they are quantifiably not simple, hence broken. In this talk I will explore the underlying causes of these problems, and propose some solutions.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"513 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2006-03-27","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123432369","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IP Quality: A New Model that Faces Methodology and Management Challenges","authors":"Kurt A. Wolf","doi":"10.1109/ISQED.2005.70","DOIUrl":"https://doi.org/10.1109/ISQED.2005.70","url":null,"abstract":"Summary form only given. The promised value and productivity from re-aggregating the IC design chain is not always delivered, in part because of isolated IP product development/quality related practices, and in part because of an inability, from a design management perspective, to see \"big picture\" issues in the IP marketplace. However these challenges are not insurmountable. The concern over IP quality has rightfully grown over the past years as the future growth of the IC industry depends on two factors; (a) achieving higher levels of design productivity; and (b) shifting internal resources towards creating and delivering value-added user benefits that stimulate increased end-product consumption. While the second factor is not discussed in this presentation, there is a presumption that higher IP quality and productivity enables a shift of resources to more application-oriented design. A pre-requisite to achieving the productivity gains is substantial improvements in the level of IP quality, coupled with increased forethought during product development. This presentation describes a methodology to evaluate IP for SoC integration. The focus is on development and quality verification practices that also account for the issues of IP integration. Additionally, the long-term growth of the semiconductor industry may be limited by the lack of value placed on collaboration, support, quality verification, and due diligence between SoC design teams and their IP partners. This presentation also describes improvements in the hard IP business relationship between these groups that enable dramatic growth through slight changes in communications models. By developing reasonable expectations and focusing on open discussion between each group, perspective begins to shift. The true value of the design team and IP partnership is a function of successful collaborations - not when the user squeezes the last drop out of NRE, royalty, per-use, or other financing models. And the value-add of the partnership is realized when that collaboration includes additional real, shared incentives that more fully value the IP industry, rather than focus on purely lowest cost.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131218524","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"SoC Engineering Trends as Impacted by New Applications and System Level Requirements","authors":"B. Candaele","doi":"10.1109/ISQED.2005.111","DOIUrl":"https://doi.org/10.1109/ISQED.2005.111","url":null,"abstract":"Summary form only given. The SoC increasing integration scale as well as the system and customer requirements are important factors for a complete revisit of the development models for electronic products. New customer models ask for software driven electronics. Software engineering is moving to a component-based and MDA development approach to be applied to embedded applications. Hardware engineering is moving to SSDI system level development and reuse methodologies. The two approaches have now to be further developed and combined for next generation SoC to get high quality and adaptable designs at a reasonable development cost. New application-level quality standards have also to be part of the complete development flow. We demonstrated through several examples these new methodologies: system engineering methodology on software radios (UML, PIM (platform independent model) and PSM (platform specific model)) and its current extension to the hardware parts (SCA, OCP potential extensions), system engineering in line with the common criteria development and qualification process for new security products (PP (protection profile) and ST (security target)), development and validation methodology in line with DO254 standard for new safety products in avionics (formal verification). Impacts on SoC architectures and design techniques are discussed.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"30 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131806601","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Enabling True Design for Manufacturability","authors":"J. Kibarian","doi":"10.1109/ISQED.2005.52","DOIUrl":"https://doi.org/10.1109/ISQED.2005.52","url":null,"abstract":"Summary form only given. Without any doubt, design-for-manufacturability (DFM) has been the hottest buzzword for the last couple of years. This is quite justifiable by the enormous challenges in nanometer technology nodes and ever increasing design-process interactions. As a result, virtually all EDA companies have focused on providing \"DFM solutions\". Since the concept of DFM covers an extremely broad spectrum of tasks, from the system level all the way to the manufacturing process, many of these DFM solutions are just design verification tasks re-labeled. We provide a more thorough classification of various DFM activities with emphasis on the design tasks. We also discuss the necessary condition to enable true DFM, i.e., the comprehensive characterization of the design-process interactions. We present a complete process characterization methodology that is capable of extracting all the salient process variations for a full set of product design attributes. We illustrate our talk by showing the yield loss Pareto for the leading technology nodes that cover all the dominant yield loss phenomena, including random, systematic and parametric mechanisms. We also demonstrate examples of design flows that take advantage of such a comprehensive characterization together with silicon results demonstrating the advantages of true DFM.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"123 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133363359","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Shifting Perspective on DFM","authors":"Joseph Sawicki","doi":"10.1109/ISQED.2005.109","DOIUrl":"https://doi.org/10.1109/ISQED.2005.109","url":null,"abstract":"Summary form only given. There is one universal truth in terms of design for manufacturing (DFM) - DFM tools and disciplines have always existed. In micron technologies, DFM methodologies were applied to ensure acceptable yield and adequate test coverage. However, nanometer technology has ushered in new and significant yield and manufacturing considerations and constraints. The lack of a major increase in yield improvement between the 350 nm and 180 nm nodes suggests that yield loss mechanisms are not only increasing, but they are increasing fast enough that 'cosmetic' improvements in tools and methodologies are largely offset. If EDA tools are to assist the semiconductor industry at the 90 nm and 65 nm nodes, there must be profound changes to existing tools, and the introduction of new technologies that allow designers to consider and optimize for manufacturing at each stage of the design, verification, tapeout and test process. Where will these new tools and capabilities appear? They will show up in all parts of the design flow, and also on the manufacturing floor. In particular, an immediate focus for the EDA industry must be to deliver new technology in four key areas: process modeling (electrical and lithographic); statistical analysis and visualization; design optimization; test and inspection.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"125 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117032638","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Quality and EDA","authors":"A. Fujimura","doi":"10.1109/ISQED.2005.100","DOIUrl":"https://doi.org/10.1109/ISQED.2005.100","url":null,"abstract":"Summary form only given. Quality has many definitions: conformance to specifications; customer satisfaction; delivery divided by expectations; etc. EDA's sense of quality is determined by what its customers want. Do we have a virtuous cycle in the quality relationship between EDA and its customers? EDA is also the quality tools supplier to help the electronics systems and semiconductor companies to produce quality products on time. The paper examines both aspects of the quality issue from an EDA perspective.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"111 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124890115","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Recent Progress and Remaining Challenges in Pattern Transfer Technologies for Advanced Chip Designs","authors":"A. Sinha","doi":"10.1109/ISQED.2005.101","DOIUrl":"https://doi.org/10.1109/ISQED.2005.101","url":null,"abstract":"Summary form only given. Even as Moore's law continues to drive \"tiny technologies\" through relentless scaling, the main technology driver for semiconductor chips has evolved from DRAMs to microprocessors to FPGAs. The underlying metrics have evolved from bits per chip and cost per bit for computers to functions per chip and cost per function for consumer products. The talk reviews the remarkable progress that has been made in enabling pattern transfer technologies, including mask design, lithography enhancements and precision etching, on the new 300 mm wafers for an increasingly wide variety of new materials. However, there is a cost associated with all this and the cost-benefit tradeoffs will almost certainly drive new inflections in the entire food chain, which the author tries to identify.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116576700","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}