{"title":"IP Quality: A New Model that Faces Methodology and Management Challenges","authors":"Kurt A. Wolf","doi":"10.1109/ISQED.2005.70","DOIUrl":null,"url":null,"abstract":"Summary form only given. The promised value and productivity from re-aggregating the IC design chain is not always delivered, in part because of isolated IP product development/quality related practices, and in part because of an inability, from a design management perspective, to see \"big picture\" issues in the IP marketplace. However these challenges are not insurmountable. The concern over IP quality has rightfully grown over the past years as the future growth of the IC industry depends on two factors; (a) achieving higher levels of design productivity; and (b) shifting internal resources towards creating and delivering value-added user benefits that stimulate increased end-product consumption. While the second factor is not discussed in this presentation, there is a presumption that higher IP quality and productivity enables a shift of resources to more application-oriented design. A pre-requisite to achieving the productivity gains is substantial improvements in the level of IP quality, coupled with increased forethought during product development. This presentation describes a methodology to evaluate IP for SoC integration. The focus is on development and quality verification practices that also account for the issues of IP integration. Additionally, the long-term growth of the semiconductor industry may be limited by the lack of value placed on collaboration, support, quality verification, and due diligence between SoC design teams and their IP partners. This presentation also describes improvements in the hard IP business relationship between these groups that enable dramatic growth through slight changes in communications models. By developing reasonable expectations and focusing on open discussion between each group, perspective begins to shift. The true value of the design team and IP partnership is a function of successful collaborations - not when the user squeezes the last drop out of NRE, royalty, per-use, or other financing models. And the value-add of the partnership is realized when that collaboration includes additional real, shared incentives that more fully value the IP industry, rather than focus on purely lowest cost.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2005-03-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2005.70","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Summary form only given. The promised value and productivity from re-aggregating the IC design chain is not always delivered, in part because of isolated IP product development/quality related practices, and in part because of an inability, from a design management perspective, to see "big picture" issues in the IP marketplace. However these challenges are not insurmountable. The concern over IP quality has rightfully grown over the past years as the future growth of the IC industry depends on two factors; (a) achieving higher levels of design productivity; and (b) shifting internal resources towards creating and delivering value-added user benefits that stimulate increased end-product consumption. While the second factor is not discussed in this presentation, there is a presumption that higher IP quality and productivity enables a shift of resources to more application-oriented design. A pre-requisite to achieving the productivity gains is substantial improvements in the level of IP quality, coupled with increased forethought during product development. This presentation describes a methodology to evaluate IP for SoC integration. The focus is on development and quality verification practices that also account for the issues of IP integration. Additionally, the long-term growth of the semiconductor industry may be limited by the lack of value placed on collaboration, support, quality verification, and due diligence between SoC design teams and their IP partners. This presentation also describes improvements in the hard IP business relationship between these groups that enable dramatic growth through slight changes in communications models. By developing reasonable expectations and focusing on open discussion between each group, perspective begins to shift. The true value of the design team and IP partnership is a function of successful collaborations - not when the user squeezes the last drop out of NRE, royalty, per-use, or other financing models. And the value-add of the partnership is realized when that collaboration includes additional real, shared incentives that more fully value the IP industry, rather than focus on purely lowest cost.