Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations

Abstract

This manuscript investigates the performance of HJ-ADG-DLTFET considering temperature variations from 200 K-500 K and by varying Interface Trap Charges (ITC) density of negative (NITC) as well as positive polarity (PITC) by utilizing Silvaco ATLAS. This is done by evaluating analog/RF performance parameters such as transconductance $(\mathrm{g}_{\mathrm{m}})$, cut-off frequency $(\mathrm{f}_{\mathrm{T}})$ and Device efficiency (DE). Furthermore, temperature variations for the range from 200-500 K demonstrate the degradation of the off-state current of HJ-ADGDLTFET. Also, DE enhances at low temperatures.