{"title":"考虑温度和ITC变化的Si/Ge异质结非对称双栅DLTFET性能研究","authors":"Suruchi Sharma, R. Basu, B. Kaur","doi":"10.1109/ISQED51717.2021.9424354","DOIUrl":null,"url":null,"abstract":"This manuscript investigates the performance of HJ-ADG-DLTFET considering temperature variations from 200 K-500 K and by varying Interface Trap Charges (ITC) density of negative (NITC) as well as positive polarity (PITC) by utilizing Silvaco ATLAS. This is done by evaluating analog/RF performance parameters such as transconductance $(\\mathrm{g}_{\\mathrm{m}})$, cut-off frequency $(\\mathrm{f}_{\\mathrm{T}})$ and Device efficiency (DE). Furthermore, temperature variations for the range from 200-500 K demonstrate the degradation of the off-state current of HJ-ADGDLTFET. Also, DE enhances at low temperatures.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"146 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2021-04-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations\",\"authors\":\"Suruchi Sharma, R. Basu, B. Kaur\",\"doi\":\"10.1109/ISQED51717.2021.9424354\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"This manuscript investigates the performance of HJ-ADG-DLTFET considering temperature variations from 200 K-500 K and by varying Interface Trap Charges (ITC) density of negative (NITC) as well as positive polarity (PITC) by utilizing Silvaco ATLAS. This is done by evaluating analog/RF performance parameters such as transconductance $(\\\\mathrm{g}_{\\\\mathrm{m}})$, cut-off frequency $(\\\\mathrm{f}_{\\\\mathrm{T}})$ and Device efficiency (DE). Furthermore, temperature variations for the range from 200-500 K demonstrate the degradation of the off-state current of HJ-ADGDLTFET. Also, DE enhances at low temperatures.\",\"PeriodicalId\":302936,\"journal\":{\"name\":\"IEEE International Symposium on Quality Electronic Design\",\"volume\":\"146 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"2021-04-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED51717.2021.9424354\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED51717.2021.9424354","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
Performance Investigation of a Si/Ge Heterojunction Asymmetric Double Gate DLTFET Considering Temperature and ITC Variations
This manuscript investigates the performance of HJ-ADG-DLTFET considering temperature variations from 200 K-500 K and by varying Interface Trap Charges (ITC) density of negative (NITC) as well as positive polarity (PITC) by utilizing Silvaco ATLAS. This is done by evaluating analog/RF performance parameters such as transconductance $(\mathrm{g}_{\mathrm{m}})$, cut-off frequency $(\mathrm{f}_{\mathrm{T}})$ and Device efficiency (DE). Furthermore, temperature variations for the range from 200-500 K demonstrate the degradation of the off-state current of HJ-ADGDLTFET. Also, DE enhances at low temperatures.
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