IEEE International Symposium on Quality Electronic Design最新文献

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Design Metrics to Achieve Design Quality 实现设计质量的设计度量
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10004
A. Kahng, R. Collett, Ton. H. van de Kraats
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引用次数: 0
Accurate architecture-level thermal analysis methods for MPSoC with consideration for leakage power dependence on temperature 考虑泄漏功率对温度依赖的MPSoC精确的架构级热分析方法
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2013.6523607
Jiaqi Yan, Zuying Luo, L. Tang
{"title":"Accurate architecture-level thermal analysis methods for MPSoC with consideration for leakage power dependence on temperature","authors":"Jiaqi Yan, Zuying Luo, L. Tang","doi":"10.1109/ISQED.2013.6523607","DOIUrl":"https://doi.org/10.1109/ISQED.2013.6523607","url":null,"abstract":"Efficient thermal analysis plays a key role in the temperature-aware floorplan design for MultiProcessor System-on-Chip (MPSoC) and Dynamic Power& Temperature Management (DPTM). This work adopts the bottom-up modeling method to study architecture-level MPSoC thermal analysis. First, it extracts relative thermal resistance between functional modules with HotSpot software. Then, based on these parameters, this work further proposes three analysis methods with different accuracy and algorithm complexity: Block-level Temperature Analysis Method (BloTAM), Core-level Temperature Analysis Method (CorTAM) and Block-Improving Core Temperature Analysis Method (BiCorTAM). Experiments show that BloTAM and BiCorTAM can substantially reduce the time for MPSoC thermal analysis with the high accuracy. Compared with HotSpot, both methods achieve 50+ times speedup in analysis with average temperature error as low as 3%. They are ideal architecture-level thermal analysis method for MPSoCs.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126710467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
An EDA Perspective, "We Need it Yesterday! 从EDA的角度来看,“我们需要它昨天!”
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2003.10023
A. Fontanelli
{"title":"An EDA Perspective, \"We Need it Yesterday!","authors":"A. Fontanelli","doi":"10.1109/ISQED.2003.10023","DOIUrl":"https://doi.org/10.1109/ISQED.2003.10023","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126300337","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The 50-Million Transistor Chip: The Quality Challenge for 2001 5000万晶体管芯片:2001年的质量挑战
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10008
R. Merritt, R. Goering
{"title":"The 50-Million Transistor Chip: The Quality Challenge for 2001","authors":"R. Merritt, R. Goering","doi":"10.1109/ISQED.2001.10008","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10008","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125765872","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Quality Aspects of SOI Circuit Design (Tutorial Abstract) SOI电路设计的质量问题(教学摘要)
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10004
A. Marshall
{"title":"Quality Aspects of SOI Circuit Design (Tutorial Abstract)","authors":"A. Marshall","doi":"10.1109/ISQED.2002.10004","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10004","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"85 1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133958502","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Semiconductors for the next wave in Automotive 下一波汽车行业的半导体
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424253
Clara Otero Pereza
{"title":"Semiconductors for the next wave in Automotive","authors":"Clara Otero Pereza","doi":"10.1109/ISQED51717.2021.9424253","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424253","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131230382","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Infineon Platform for SoC IO Ring and Package Design 英飞凌SoC IO环和封装设计平台
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424351
Sathvik Tarikere Sathyanarayana, Anna-Antonia Berger, M. Kumar, A. Erkan, Ramkrishna Paira
{"title":"Infineon Platform for SoC IO Ring and Package Design","authors":"Sathvik Tarikere Sathyanarayana, Anna-Antonia Berger, M. Kumar, A. Erkan, Ramkrishna Paira","doi":"10.1109/ISQED51717.2021.9424351","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424351","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131256866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Supplemental Test Methods (Tutorial Abstract) 补充测试方法(教程摘要)
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2002.10033
S. Chakravarty
{"title":"Supplemental Test Methods (Tutorial Abstract)","authors":"S. Chakravarty","doi":"10.1109/ISQED.2002.10033","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10033","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117228367","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Redundancy Requirements for Embedded Memories 嵌入式存储器的冗余要求
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2001.10002
M. Tamjidi, B. Oomman
{"title":"Redundancy Requirements for Embedded Memories","authors":"M. Tamjidi, B. Oomman","doi":"10.1109/ISQED.2001.10002","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10002","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"192 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123522400","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
NBTI/HCI Modeling and Full-Chip Analysis in Design Environment 设计环境下的NBTI/HCI建模与全芯片分析
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2003.10002
Lifeng Wu
{"title":"NBTI/HCI Modeling and Full-Chip Analysis in Design Environment","authors":"Lifeng Wu","doi":"10.1109/ISQED.2003.10002","DOIUrl":"https://doi.org/10.1109/ISQED.2003.10002","url":null,"abstract":"Hot-carrier (HC) degradation and negative bias temperature instability (NBTI) of MOS devices are the two most important reliability concerns for deep submicron (DSM) designs. HC degradation occurs when the channel electrons are accelerated in the high electric field near the drain of the MOS device and create interface states, electron traps, or hole traps in the gate oxide near the drain. LDD structure has become the standard drain structure to alleviate HC effects and the device-based DC criteria have been used extensively to qualify devices for HC reliability. It is becoming clear that these guidelines are too conservative for DSM technologies. It is therefore strongly desirable that circuit reliability simulation using a realistic AC (transient) circuit operation condition should be on the fingertips of the circuit designers to achieve the following goals: to maximize design performance by minimizing design guard-band, to speed up timing closure by reducing design iterations and to ensure circuit reliability by fixing design reliability problems. How to fit reliability simulation into the design environment is a more interesting topic from designer’s perspective.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129368171","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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