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Slap it Together and Ship it! 把它们组装在一起，然后发货!
IEEE International Symposium on Quality Electronic Design Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.10015
A. Geus
{"title":"Slap it Together and Ship it!","authors":"A. Geus","doi":"10.1109/ISQED.2000.10015","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10015","url":null,"abstract":"In today's world of e-commerce and dot-com instant business successes, time to market constraints have taken the upper hand in almost all product decisions. In that scenario, what happens to the role of quality in the design of semiconductors and electronic systems? In this keynote, Aart de Geus addresses the trade-offs of if market's needs vs. is quality's needs and shows that what appears to be a trade-off may not be one at all.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132618847","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
The Practical Side of Quality 质量的实用面
IEEE International Symposium on Quality Electronic Design Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.10005
J. East
{"title":"The Practical Side of Quality","authors":"J. East","doi":"10.1109/ISQED.2000.10005","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10005","url":null,"abstract":"My practical definition of quality is getting it right the first time, on time. The downsides of poor quality work need no explanation. Unfortunately, though, the consequences of being late to market can doom any potential market advantage. The only sure win comes when the product is both high quality and on time. To help assure on-time delivery of working ICs, I advocate \"two-handed management\". This means with one hand, do the job as best you can using the tools and techniques available, but with the other hand, take steps to see similar jobs are done better and faster the next time. An example of two-handed management in the distant past was the development of various simulation techniques. The two-handed manager of the future will look for silicon with advanced capabilities in the areas of \"observability,\" \"tweakability\" and incremental specification techniques as well as inherent improvements in speed, power and cost.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117054034","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Focus on Quality of Design: Does it Help or Hinder Time to Market? 关注设计质量:是帮助还是阻碍上市时间?
IEEE International Symposium on Quality Electronic Design Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.10010
N. Vasseghi, R. Glover
{"title":"Focus on Quality of Design: Does it Help or Hinder Time to Market?","authors":"N. Vasseghi, R. Glover","doi":"10.1109/ISQED.2000.10010","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10010","url":null,"abstract":"The ability to deliver high quality products on time has become increasingly important in today's competitive environment. Speed and time to market, are the new competitive weapons. The ability to accelerate products from concept to production, and ahead of the competition, is more than ever central to success.So, what is the shortest path from concept to production? One school of thought is to focus on total quality along the way with an aim to ensure that the first product is fully functional and as close to production worthy as possible. This usually means following systematic product development processes with detailed quality check points and gate reviews built-in at every stage.On the other hand, some view this as too much of bureaucracy, rules, and restrictions that slow down and hinder the first introduction of the product to market. This point of view believes in getting the product out as soon as possible to get the necessary technical and marketing validations early, and then continue on improving and polishing the product to make it production worthy.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130438116","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design for Quality and Manufacturing 为质量和制造设计
IEEE International Symposium on Quality Electronic Design Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.10018
Prakash Agrawal
{"title":"Design for Quality and Manufacturing","authors":"Prakash Agrawal","doi":"10.1109/ISQED.2000.10018","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10018","url":null,"abstract":"This presentation will discuss from a CEO's perspective the process needed to design a quality chip for manufacturing. It will cover the milestones necessary for bringing a successful chip to market. Discussion highlights will focus first on a well thought out analysis of market requirements, taking into account the product roadmaps and feature requirements of your major customers, the competition, the potential market size, and the delivery schedule necessary to hit the window of opportunity to sell the new product. Next, it will focus on how to proceed with a thorough evaluation of your company's internal variables, such as your technology roadmap, cost analysis, capability of strategic partners, capacity requirements, and return on investment. Finally, it will give tips on evaluating the results of matching the market requirements with your company's internal capabilities. It will mention some of the well-known design tools and practices used in the industry that can help you assure the built-in quality necessary to meet manufacturing standards and market needs.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123708025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Deep Submicron USLI Design Paradigm: Who is Writing the Future? 深亚微米USLI设计范式:谁在书写未来?
IEEE International Symposium on Quality Electronic Design Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.10014
K. Eshraghian
{"title":"Deep Submicron USLI Design Paradigm: Who is Writing the Future?","authors":"K. Eshraghian","doi":"10.1109/ISQED.2000.10014","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10014","url":null,"abstract":"The concept of \"technology generation\" attributed to Gordon Moore has created a plausible method for predicting the behavior of technology road map that has seen world's production of silicon CMOS to exceed 75% of electronic related materials. A feature of such progress is characterized by the complexity factor that predicts the emergence of a new generation of technology every three years.A reasonable method of comparison would be to observe the parallel between CMOS based systems with those of biologically inspired systems. Deep submicron, synonymous with Ultra Large Scale of integration, suggests that by the year 2010 the number of transistors/chip will be in the order of 0.5x10 9 , with an intrinsic clock speed of 3GHz. At this level of integration the classic MOS transistor would have only a few ?electrons' in the channel to direct. Thus, the reality of Quantum MOS (QMOS) transistor becomes a plausible possibility.In the mean time the question remains as to how are we going to cope with the design and quality of the new system complexity. ULSI design requires a shift in the design paradigm from current evolutionary thinking for system integration, to more of revolutionary approaches as depicted by attributes of if brain architecture.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"58 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116997693","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Embedded-Quality for Test 嵌入式质量测试
IEEE International Symposium on Quality Electronic Design Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.10008
Y. Zorian
{"title":"Embedded-Quality for Test","authors":"Y. Zorian","doi":"10.1109/ISQED.2000.10008","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10008","url":null,"abstract":"The basic concept of embedding test functions onto the very IC design is a simple one. However, the complexity offered by the emerging system-on-chip and the very deep micron technologies has created difficult challenges and quality risks. A new wave of embedded, quality insurance functions, are needed to address this complexity level. This talk will discuss such design for quality trends and solutions and will analyze their impact not only on go/no-go test, but also on a set of expanded quality insurance functions to support debug, measurement, diagnosis and repair.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"42 6","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120891310","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Efficient Delay Calculation in Presence of Crosstalk 串扰存在下的有效延迟计算
IEEE International Symposium on Quality Electronic Design Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.838932
Tong Xiao, M. Marek-Sadowska
{"title":"Efficient Delay Calculation in Presence of Crosstalk","authors":"Tong Xiao, M. Marek-Sadowska","doi":"10.1109/ISQED.2000.838932","DOIUrl":"https://doi.org/10.1109/ISQED.2000.838932","url":null,"abstract":"Efficient and accurate delay calculation is very important in physical design, optimization and fast verification. In this paper we consider explicit delay calculation for RC interconnects with coupling capacitance. The formulae are derived using a simplified transfer function which offers enough accuracy. We have expressed coefficients of two pole transfer function in terms of circuit parameters. Moment matching methods do not yield such explicit expressions. Our simplified delay calculation method is most suitable in physical design and fast timing verification where the dependency of delay on circuit parameters is essential.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131777150","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead? 深亚微米的设计-制造界面:技术独立设计已死吗?
IEEE International Symposium on Quality Electronic Design Pub Date : 2000-03-20 DOI: 10.1109/ISQED.2000.10000
C. Guardiani, A. Strojwas
{"title":"Design-Manufacturing Interface in the Deep Submicron: Is Technology Independent Design Dead?","authors":"C. Guardiani, A. Strojwas","doi":"10.1109/ISQED.2000.10000","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10000","url":null,"abstract":"Not so long ago, the technology independent design style was advertised as the way to go, at least for ASICs. Seamless mapping of RTL code onto pre-characterized IP libraries and automatic P&R seemed to provide a smooth path from HDL to mask layout. Unfortunately, this approach does not appear to be feasible in the deep submicron (DSM) era, especially for high performance IC's.To achieve top performance while maintaining satisfactory manufacturing yields, the technology capabilities, including quasi-transmission line effects in interconnections, must be extracted and abstracted to be used up-front in the design synthesis. The design-manufacturing interface must be changed in order to account for these DSM effects, while still being able to handle the increasing complexity of designs.This panel will address the requirements imposed on the design - manufacturing interface for the DSM technologies by gathering experts from the different segments of the semiconductor industry, to address design needs versus available solutions and potential show-stoppers in designing high complexity chips for leading edge technologies.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126054747","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Novel technique for P-hit single-event transient mitigation using enhance dummy transistor 利用增强假体晶体管的p击单事件瞬态缓解新技术
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED.2015.7085433
Tianqi Wang, Liyi Xiao, Mingxue Huo, Chunhua Qi, Shanshan Liu
{"title":"Novel technique for P-hit single-event transient mitigation using enhance dummy transistor","authors":"Tianqi Wang, Liyi Xiao, Mingxue Huo, Chunhua Qi, Shanshan Liu","doi":"10.1109/ISQED.2015.7085433","DOIUrl":"https://doi.org/10.1109/ISQED.2015.7085433","url":null,"abstract":"As technology down scales, single event transient (SET) is more vulnerable than before in combinational circuits. This paper proposes a novel layout technique to mitigate the SET effect in combinational circuits. Based on 65nm CMOS process, technology computer aided design (TCAD) SET simulations are conducted on conventional layout, source-isolation layout, dummy transistor layout and the proposed layout. Heavy ions with different liner energy transfer (LET) values, inject angles and striking locations are simulated. The results indicate that, the proposed layout have considerable effect on decreasing the SET pulse width than other layouts. Compare with dummy transistor the proposed enhance dummy transistor have no additional area cost.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114517387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric 基于铌基超导硅互连结构的大规模量子系统设计
IEEE International Symposium on Quality Electronic Design Pub Date : 1900-01-01 DOI: 10.1109/ISQED51717.2021.9424295
Yu-Tao Yang, S. Iyer
{"title":"Large-Scale Quantum System Design on Nb-based Superconducting Silicon Interconnect Fabric","authors":"Yu-Tao Yang, S. Iyer","doi":"10.1109/ISQED51717.2021.9424295","DOIUrl":"https://doi.org/10.1109/ISQED51717.2021.9424295","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121916949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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