IEEE International Symposium on Quality Electronic Design最新文献

{"title":"Efficient Closed-Form Crosstalk Delay Metrics","authors":"L. Chen, M. Marek-Sadowska","doi":"10.1109/ISQED.2002.996784","DOIUrl":"https://doi.org/10.1109/ISQED.2002.996784","url":null,"abstract":"In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced delay in distributed RC coupling network. The efficiency of our approach stems from the fact that only five basic operations are used in the expressions: addition, subtraction, multiplication, division, and square root. The formulas do not require exponent computation or numerical iterations. Our estimates are conservative, and yet achieve acceptable accuracy. They are simple enough to be used in the inner loops of performance optimization or as cost functions for a router. The delay expressions capture the dependency on coupling direction and coupling location.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"11 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116907085","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IP REUSE QUALITY: \"Intellectual Property\" or \"Intense Pain\"?","authors":"J. Chilton","doi":"10.1109/ISQED.2002.10024","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10024","url":null,"abstract":"As systems on a chip become more complex, reuse of third-party intellectual property (IP) becomes more necessary to meet time-to-market deadlines. However, issues surrounding IP quality are very much unresolved. Poor IP quality is the key reason why many IP users feel that “IP” is actually an acronym for “Intense Pain.” . There are major inconsistencies surrounding basic quality, including fully synchronous design, registered inputs and outputs for IP blocks, and completion of full specifications before design. All these inconsistencies contribute to difficulties in using the IP and integrating it into a chip design. One of the key reasons why quality is still such an issue within the IP community is the issue of “reuse” versus “salvaging.” Much of the IP sold over the last few years wasn’t really designed for reuse. Instead, it was designed for use in a single chip, then later repackaged (i.e., salvaged) as IP. There has also been tremendous interest in creating IP repositories—fancy Java-based, Web-accessed, and multi-featured custom products meant to hold the wealth of IP. Along the way, though, we forgot to create enough fully reusable IP to warrant these repository investments. Although the challenges in the IP business may seem daunting (and there are many more besides just those that concern quality), they are well worth the effort when you consider the rewards. There’s a tremendous need for IP to address the growing productivity gap, which represents a great opportunity for the third-party IP industry.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"14 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124163679","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Design Success: Foundry Perspective","authors":"J. Kupec","doi":"10.1109/ISQED.2002.10030","DOIUrl":"https://doi.org/10.1109/ISQED.2002.10030","url":null,"abstract":"Leading edge foundries are rolling out new process technologies every two years with today’s advance processes capable of producing a quarter billion transistor on a thumb-nail sized chip. The growth of the fabless business model has enabled many companies to organize and build value with the strength of their design capabilities. Quality is often reflected by the continued success of design practices resulting in market success. The many styles of design implementations provided by a large number of companies sharing a common process helps provide a Darwinian view of quality practices. The interaction with design flows, libraries, special purpose IP, memory types are important considerations. This talk will address the trade-offs and successful design technologies used in foundries.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"70 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2002-03-18","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134590281","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"IC Design Methodology in the Foundry Era: Introducing , Heads-Up(tm) Design","authors":"E. C. Ross","doi":"10.1109/ISQED.2001.10009","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10009","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"78 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127295947","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Delivering Quality Delivers Profits","authors":"J. Costello","doi":"10.1109/ISQED.2001.10010","DOIUrl":"https://doi.org/10.1109/ISQED.2001.10010","url":null,"abstract":"","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"59 17 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2001-03-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123873745","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"The Hidden Costs of Design Qualit","authors":"R. Goering, Richard Wallace","doi":"10.1109/ISQED.2000.10007","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10007","url":null,"abstract":"This high-level panel will look at importantbut often overlookedglobal, social and economic implications of design quality. It will probe the costs, to both end users and manufacturers, of poor quality. Only by accounting for these costs can manufacturers gauge the importance of proper verification and design techniques.The goal of this panel is to identify some of the quality-related problems that could plausibly occur, discuss their consequences, and propose some solutions for improving the quality and reliability of electronic designs. This panel will also probe the question of who takes responsibility when silicon fails. Assuming that the wafer fab process is yielding correctly, and the chip is not working due to a design quality problem, then who pays what price? How is responsibility shared among systems companies, IP providers, and semiconductor manufacturers?","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"28 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114158269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Ramping New IC Products in the Deep Submicron Age","authors":"J. Kibarian","doi":"10.1109/ISQED.2000.10009","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10009","url":null,"abstract":"It is well known that the majority of the potential profits are early in a products life. This is especially true in product segments such as system on a chip, graphics accelerators, microprocessors, and memory. The spoils in these segments go the company who gets its product to market first. At the same time, the investments required to produce the next generation products is going up at an accelerated pace. As a result, companies are sharing the investment by working with more third party suppliers. Today, a chip will be designed with 3rd party EDA tools and using commercial IP. It is often manufactured in commercial foundries, and tested and assembled a separate company. When the product is not meeting yield and performance, how are the issues resolved? Eventually, these yield issues are resolved, but often not before the profitable part of the product's life-style is complete. In this presentation we describe new methodologies, tools and services, which can help, turn designs into products. We will summarize the key technical issues, which make performance and yield targets difficult to meet given the product's life-style constraints and demonstrate how these new methodologies can greatly change the production ramp. Examples of these methods applied to advanced products such as microprocessors, embedded DRAM, and system on a chip, and DRAM will be provided.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126537992","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"What is Design Quality? How can Quality in Electronic Design be Quantified?","authors":"M. Reinhardt, M. Santarini","doi":"10.1109/ISQED.2000.10002","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10002","url":null,"abstract":"Quality of an IC design can be determined by many factors like Performance, Flexibility, Reliability, Testability, Ease of Maintenance, Yield, Portability, Reusability, etc. Quality of a design has to be considered on every level of a design from RTL description down to silicon. The chip design industry has come a long way since the days when quality considerations were an ad hoc combination of collective reactions to afterthoughts and back-end control gates used as a method of screening.Today, successful design efforts are measured by how fast they can meet aggressive design schedules. A key element in achieving aggressive design schedules in a meaningful way would be to develop designs that work the first time. Quality considerations in design were first introduced as part of the structured approach to VLSI design methodology more than a decade ago. Along with it came generic recommendations, rules and mandates that equally applied to all design practices with the goal of making the design process more predictable. All of this came at a price that included power, area and performance. Because of these drawbacks, the standard products industry (none-ASIC) continued to use ad hoc design methods instead of using a more streamlined and structured approach.Technology scaling into deep sub-micron and the growing design complexity has required many aspects of design flow and design methodology to become more design specific. Once known as bullet- proof methods in design have given way to more flexible implementation choices based on performance optimization goals and other necessary design tradeoffs. The sharp distinction that once existed between ASSP and ASIC designs has become somewhat blurred promising the difference will disappear altogether in a near future. Irrespective to their implementation methods, designs are expected to become increasingly more predictable and take less time to do. The bottom line for most design or semiconductor companies is how many engineering dollars need to be invested in a given design to create a maximum in revenue and more important in earnings.Therefore in the era of SOC design the quality of a design cannot only be determined whether the design meets the specification or not. The new quality criteria are related to the total costs a design creates during its entire lifetime. The longer a design stays alive or the more reincarnations it has in various silicon systems the more income a design can create. Factors like Reliability, Flexibility, Portability or Reusability are becoming more and more important for the success of a design. Experts from semiconductor companies, fabless design houses; EDA vendor and universities discuss what has to happen or what they do to ensure quality of their designs in an economic way.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114062008","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"Platform-Based Design: A Path to Efficient Design Re-Use","authors":"A. Sangiovanni-Vincentelli","doi":"10.1109/ISQED.2000.10011","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10011","url":null,"abstract":"System design is undergoing a series of radical transformations to meet performance, quality, safety, cost and time-to-market constraints introduced by the pervasive use of electronics in everyday objects. An essential component of the new system design paradigm is the orthogonalization of concerns, i.e., the separation of the various aspects of design to allow more effective exploration of alternative solutions. Since the mask set and design cost for Deep Sub-Micron implementations is predicted to be overwhelming, it is important to find common architectures that can support a variety of applications. In this talk, we will explore methods for selecting families of software and hardware architectures that allow a substantial design re-use and some paradigms for embedded system designs that are likely to become the pillars of future tools and flows.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"2 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128173731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

{"title":"How Do You Select A High Quality EDA Tool Flow?","authors":"Robert N. Blair, J. Benkoski","doi":"10.1109/ISQED.2000.10003","DOIUrl":"https://doi.org/10.1109/ISQED.2000.10003","url":null,"abstract":"Over the last 10 years, Integrated circuits complexity has blossomed to the point where system time to market is critically dependant on IC \"correctness\" as intended by the \"designer\". In many cases, the \"designer\" is a team of engineers - not an individual, and the \"tools\" are a flow - not a series of point tools. To a first approximation, the industry wafer fabrication process has achieved a level of \"correctness\", or \"quality\" that exceeds that of the EDA tools being used to create and implement the IC design. Integrated EDA tools lag behind Moore's law, and are the primary cause of the \"non-correctness\" being experienced with many complex IC designs today. The EDA industry needs to unify behind new \"high quality design flow\" criteria that the user community believes in and can integrate into established system design environments. One of the critical issues facing the design community is how to select a high quality EDA design tool flow in this environment, and what should EDA tool providers do to close the gap with Moore's Law?","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2000-03-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134226796","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}