Nanoelectronics: Evolution or Revolution?

Scaling of CMOS technology continues in spite of tremendous technology development barriers, design challenges and prohibitive costs. Today, the 65nm CMOS technology node is moving from development to high volume manufacturing while research and development continues on future technology nodes including 45nm, 30nm and beyond. Design of ICs in these scaled technologies faces new limitations. It is increasingly difficult to sustain supply and threshold voltage scaling to provide the required performance increase, limit energy consumption, control power dissipation, and maintain reliability. These requirements pose several difficulties across a range of disciplines spanning technology, fabrication, transistor structure, circuits, systems, design, and architecture. On the technology front, the question arises whether we can continue to scale CMOS technology and whether we are close to the end of the ITRS roadmap. Are there any fundamental barriers? Should we continue along the traditional CMOS scaling path reduce effective oxide thickness, improve channel mobility, and minimize parasitic or consider a more radical departure from planar CMOS to non-planar device structures such as tri-gate and FinFET thin body transistors? Will we ever use nanowires and other novel nano devices such as Carbon nanotubes and self-assembled molecular devices? How important is self-assembly and bottom-up manufacturing in making future systems? What options do we have post non-planar CMOS and before more exotic spintronics and quantum devices? On the design front, while researchers are addressing various circuit design techniques to deal with process variation and leakage, it is unclear whether we can build systems with non-planar CMOS devices and other novel nano devices. Do we need new circuit design methods? How do we put systems together either with aggressively scaled Si devices, non-planar CMOS or with self-assembled molecular devices? What are the implications for design community? Will the information processing paradigm shift? Will we learn anything from researching futuristic nanoscale devices, circuits and systems that may impact scaling of Silicon CMOS technology?