{"title":"0.13微米:减速带会减缓市场竞争吗?","authors":"B. Alexander, J. Benkoski","doi":"10.1109/ISQED.2001.10018","DOIUrl":null,"url":null,"abstract":"Description Engineering departments face spiraling expectations to deliver more sophisticated products in less time while coping with the challenges of cutting-edge 0.13 micron technology. Are the tools and methods ready and available to allow the shift to 0.13? Are designers prepared and armed to make 0.13 a mainstream production technology in an economical way within the next 24 months? In the past the next process technologies were brought up to volume production by shrinking existing circuit designs to the new technology. Will this approach work or is it necessary develop all circuits new for 0.13 micron? In 0.13 micron technologies designers, CAD developers and manufacturers are faced with effects like following: Digital designs are beginning to behave like analog circuits. Physical phenomenon, which were not important before, need to be taken into consideration. Timing and noise are becoming intertwined. Design rules are more complex and don’t shrink linearly. New optical effects for masks, yield issues, etc., etc. As the traditional methods are not working any more to shift existing designs to 0.13 micron technology the provocative question comes up; what are the “show stoppers” and what does it take to “let the show go on”? A panel representing system and IC designer, EDA vendors, and semiconductor manufacturing executives will share their experiences, methods, and tools that they use or provide to tackle the 0.13 micron challenges and to accelerate design productivity.","PeriodicalId":302936,"journal":{"name":"IEEE International Symposium on Quality Electronic Design","volume":"45 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"0.13 micron: Will the Speed Bumps Slow the Race to Market?\",\"authors\":\"B. Alexander, J. Benkoski\",\"doi\":\"10.1109/ISQED.2001.10018\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Description Engineering departments face spiraling expectations to deliver more sophisticated products in less time while coping with the challenges of cutting-edge 0.13 micron technology. Are the tools and methods ready and available to allow the shift to 0.13? Are designers prepared and armed to make 0.13 a mainstream production technology in an economical way within the next 24 months? In the past the next process technologies were brought up to volume production by shrinking existing circuit designs to the new technology. Will this approach work or is it necessary develop all circuits new for 0.13 micron? In 0.13 micron technologies designers, CAD developers and manufacturers are faced with effects like following: Digital designs are beginning to behave like analog circuits. Physical phenomenon, which were not important before, need to be taken into consideration. Timing and noise are becoming intertwined. Design rules are more complex and don’t shrink linearly. New optical effects for masks, yield issues, etc., etc. As the traditional methods are not working any more to shift existing designs to 0.13 micron technology the provocative question comes up; what are the “show stoppers” and what does it take to “let the show go on”? A panel representing system and IC designer, EDA vendors, and semiconductor manufacturing executives will share their experiences, methods, and tools that they use or provide to tackle the 0.13 micron challenges and to accelerate design productivity.\",\"PeriodicalId\":302936,\"journal\":{\"name\":\"IEEE International Symposium on Quality Electronic Design\",\"volume\":\"45 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1900-01-01\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"IEEE International Symposium on Quality Electronic Design\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ISQED.2001.10018\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE International Symposium on Quality Electronic Design","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ISQED.2001.10018","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
0.13 micron: Will the Speed Bumps Slow the Race to Market?
Description Engineering departments face spiraling expectations to deliver more sophisticated products in less time while coping with the challenges of cutting-edge 0.13 micron technology. Are the tools and methods ready and available to allow the shift to 0.13? Are designers prepared and armed to make 0.13 a mainstream production technology in an economical way within the next 24 months? In the past the next process technologies were brought up to volume production by shrinking existing circuit designs to the new technology. Will this approach work or is it necessary develop all circuits new for 0.13 micron? In 0.13 micron technologies designers, CAD developers and manufacturers are faced with effects like following: Digital designs are beginning to behave like analog circuits. Physical phenomenon, which were not important before, need to be taken into consideration. Timing and noise are becoming intertwined. Design rules are more complex and don’t shrink linearly. New optical effects for masks, yield issues, etc., etc. As the traditional methods are not working any more to shift existing designs to 0.13 micron technology the provocative question comes up; what are the “show stoppers” and what does it take to “let the show go on”? A panel representing system and IC designer, EDA vendors, and semiconductor manufacturing executives will share their experiences, methods, and tools that they use or provide to tackle the 0.13 micron challenges and to accelerate design productivity.