发布求助
文献互助 智能选刊 最新文献

2004 Electrical Overstress/Electrostatic Discharge Symposium最新文献

筛选
英文 中文
Wire bonding tip study for extremely ESD sensitive devices 极ESD敏感器件的导线键合尖端研究
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272641
R. Money, C. Coureau, W. Boone, A. Wallash
{"title":"Wire bonding tip study for extremely ESD sensitive devices","authors":"R. Money, C. Coureau, W. Boone, A. Wallash","doi":"10.1109/EOSESD.2004.5272641","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272641","url":null,"abstract":"Ultrasonic bonding tools are used extensively in many industries. This study will examine the mechanism of Ultrasonic wire bonding & the effects of ESD charge removal using a common ceramic material spread into 3 different resistances groups and recording the behavior. Our purpose is to examine the bonding tool's ability to control - voltage and characterize their respective dissipation rates for the purpose of determining an optimum process window. Experimentation will show the positive & negative effects of typical tools in use today as mechanical bonding tools. An analysis is shown of the effectiveness of the tip in simulating the dissipating voltage away from a floating GMR head. We will examine their ability to discharge voltage from devices and reduce ESD currents.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114521106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
From the ESD robustness of products to the system ESD robustness 从产品的ESD稳健性到系统ESD稳健性
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272634
W. Stadler, S. Bargstadt-Franke, T. Brodbeck, R. Gaertner, M. Goroll, H. Gosner, C. Jensen
{"title":"From the ESD robustness of products to the system ESD robustness","authors":"W. Stadler, S. Bargstadt-Franke, T. Brodbeck, R. Gaertner, M. Goroll, H. Gosner, C. Jensen","doi":"10.1109/EOSESD.2004.5272634","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272634","url":null,"abstract":"In this contribution a methodology is presented which allows the estimation of a system level ESD robustness from the ESD characterization on device level. The basic idea behind this methodology is that predominantly three different failure mechanisms exist. CDM-type stress (pulse duration ~1 ns) causes break down of dielectrics, e.g., gate oxides. The relevant parameter is the peak current of the discharge. Stress similar to HBM (time domain 50-200 ns) results usually in thermal damages due to the dissipated energy in the device. EOS damage (stress duration > 1 mus) are caused by thermal power forced into the device which itself is in thermal equilibrium. Examples are given where the ESD threshold voltage of system level tests on devices could be derived from the device characterization with an accuracy of 20-30 %.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"269 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132457449","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies 工程单NMOS和PMOS输出缓冲器的最大失效电压在先进的CMOS技术
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272600
M. Khazhinsky, J. Miller, M. Stockinger, J. Weldon
{"title":"Engineering single NMOS and PMOS output buffers for maximum failure voltage in advanced CMOS technologies","authors":"M. Khazhinsky, J. Miller, M. Stockinger, J. Weldon","doi":"10.1109/EOSESD.2004.5272600","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272600","url":null,"abstract":"In this paper we propose new circuit design options for increasing the ldquoeffectiverdquo failure voltage (Vt2) of both NMOS and PMOS output buffer transistors, thereby helping to protect these fragile devices. Using experimental data, device and circuit simulations we demonstrate how placing a series resistor and either a bias circuit for the buffer gates or secondary ESD diodes may significantly increase Vt2.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123634183","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
Advanced ESD rail clamp network design for high voltage CMOS applications 先进的ESD导轨钳网络设计，适用于高压CMOS应用
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272599
M. Stockinger, J. Miller
{"title":"Advanced ESD rail clamp network design for high voltage CMOS applications","authors":"M. Stockinger, J. Miller","doi":"10.1109/EOSESD.2004.5272599","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272599","url":null,"abstract":"We present a new boosted and distributed ESD rail clamp protection approach for high voltage CMOS applications using stacked active MOSFET rail clamps and provide design guidelines for practical pad ring scenarios. This approach offers improved ESD robustness, area compactness, layout modularity, process portability, scalability, and ease of simulation.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"91 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127148849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
Formation and suppression of a newly discovered secondary EOS event in HBM test systems 在HBM测试系统中新发现的二次EOS事件的形成和抑制
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272618
T. Meuse, L. Ting, J. Schichl, R. Barrett, D. Bennett, R. Cline, C. Duvvury, M. Hopkins, H. Kunz, J. Leiserson, R. Steinhoff
{"title":"Formation and suppression of a newly discovered secondary EOS event in HBM test systems","authors":"T. Meuse, L. Ting, J. Schichl, R. Barrett, D. Bennett, R. Cline, C. Duvvury, M. Hopkins, H. Kunz, J. Leiserson, R. Steinhoff","doi":"10.1109/EOSESD.2004.5272618","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272618","url":null,"abstract":"A previously undetected trailing pulse from HBM testers was found to create unexpected gate oxide failures on new technologies. This secondary pulse, which is EOS in nature, is caused by the discharge relay and the parasitics of the charge circuit. This paper investigates this critical phenomenon and establishes the tester improvements to safely suppress the trailing pulse effects.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130938530","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Notes on maintaining sub-1V balance of an ionizer 保持电离器低于1v平衡的注意事项
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272608
V. Kraz
{"title":"Notes on maintaining sub-1V balance of an ionizer","authors":"V. Kraz","doi":"10.1109/EOSESD.2004.5272608","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272608","url":null,"abstract":"This paper discusses steps necessary to undertake and technical details on setting up and maintaining sub-1V balance in the ionizeed environment. Specifics of closed-loop control are discussed. Results of tests under various conditions are presented.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"234 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133547727","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs 高压CMOS集成电路中无锁存器电源轨ESD钳位电路的设计
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272601
Kun-Hsien Lin, M. Ker
{"title":"Design on latchup-free power-rail ESD clamp circuit in high-voltage CMOS ICs","authors":"Kun-Hsien Lin, M. Ker","doi":"10.1109/EOSESD.2004.5272601","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272601","url":null,"abstract":"The holding voltage of the high-voltage ESD protection devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-mum 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with VDD of 40 V.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"13 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123851887","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 15
Comparison of thermal response of GMR sensor subjected to HBM and CDM transients GMR传感器在HBM和CDM瞬态下的热响应比较
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272586
Yizhang Yang, M. Asheghi
{"title":"Comparison of thermal response of GMR sensor subjected to HBM and CDM transients","authors":"Yizhang Yang, M. Asheghi","doi":"10.1109/EOSESD.2004.5272586","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272586","url":null,"abstract":"The thermal response of the GMR sensor during the ESD pulse is investigated using finite element model. The simulation compares the transient temperature rise in GMR sensor when they are subjected to the Human Body Model (HBM) and Charged-Device Model (CDM) waveforms. The results indicate that the ESD threshold damage for GMR head depends on both the thermal time constant and the ESD transient current.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124437997","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Improved wafer-level VFTLP system and investigation of device turn-on effects 晶片级VFTLP系统的改进及器件导通效应的研究
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272590
Junjun Li, S. Hyvonen, E. Rosenbaum
{"title":"Improved wafer-level VFTLP system and investigation of device turn-on effects","authors":"Junjun Li, S. Hyvonen, E. Rosenbaum","doi":"10.1109/EOSESD.2004.5272590","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272590","url":null,"abstract":"We present an improved wafer-level VFTLP measurement system. This system produces pulses with sub-150 ps rise time and few distortions at the rising edge. By introducing a broadband power divider, the oscilloscope no longer limits the pulse amplitude, and arbitrarily high pulse voltages can be measured. Turn-on effects in diodes and NMOSFETs are investigated using this system.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"46 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114111184","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 18
Multi-terminal pulsed force & sense ESD verification of I/O libraries and ESD simulations I/O库的多端脉冲力和传感ESD验证及ESD仿真
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 2004-09-01 DOI: 10.1109/EOSESD.2004.5272589
S. Druen, M. Streibl, K. Esmark, K. Domanski, J. Niemesheim, H. Gossner, D. Schmitt-Landsiedel
{"title":"Multi-terminal pulsed force & sense ESD verification of I/O libraries and ESD simulations","authors":"S. Druen, M. Streibl, K. Esmark, K. Domanski, J. Niemesheim, H. Gossner, D. Schmitt-Landsiedel","doi":"10.1109/EOSESD.2004.5272589","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272589","url":null,"abstract":"A multi-terminal TLP measurement technique is used for accessing current and voltage distributions during ESD in typical I/O cell frames in a 0.13 um CMOS technology. The procedure extends traditional I/O library testchip based ESD verification and qualification tests, allows to calibrate ESD chip-level simulation tools and to derive precise I/O library application rules.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"43 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2004-09-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127497637","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
下一页 尾页
0
×
引用
GB/T 7714-2015
复制
MLA
复制
APA
复制
导出至
BibTeX EndNote RefMan NoteFirst NoteExpress
×
提示
您的信息不完整，为了账户安全，请先补充。
现在去补充
×
提示
您因"违规操作"
具体请查看互助需知
我知道了
×
提示
现在去查看 取消
×
提示
确定
请完成安全验证×
相关产品
×
本文献相关产品
联系我们：info@booksci.cn Book学术提供免费学术资源搜索服务，方便国内外学者检索中英文文献。致力于提供最便捷和优质的服务体验。 Copyright © 2023 布克学术 All rights reserved.
京ICP备2023020795号-1
ghs 京公网安备 11010802042870号
Book学术文献互助
Book学术文献互助群
群 号：481959085
Book学术官方微信