Multi-terminal pulsed force & sense ESD verification of I/O libraries and ESD simulations

Abstract

A multi-terminal TLP measurement technique is used for accessing current and voltage distributions during ESD in typical I/O cell frames in a 0.13 um CMOS technology. The procedure extends traditional I/O library testchip based ESD verification and qualification tests, allows to calibrate ESD chip-level simulation tools and to derive precise I/O library application rules.