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Multilevel Transmission Line Pulse (MTLP) tester 多级传输线脉冲(MTLP)测试仪
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 1900-01-01 DOI: 10.1109/EOSESD.2004.5272592
T. Daenen, S. Thijs, M. Natarajan, V. Vassilev, V. De Heyn, G. Groeseneken
{"title":"Multilevel Transmission Line Pulse (MTLP) tester","authors":"T. Daenen, S. Thijs, M. Natarajan, V. Vassilev, V. De Heyn, G. Groeseneken","doi":"10.1109/EOSESD.2004.5272592","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272592","url":null,"abstract":"A novel TLP testing approach, multilevel TLP (MTLP), is described, which can yield accurate and comprehensive snapback IV measurements unlike in the conventional TLP testing methodology with different system impedances. The experimental validity of the MTLP methodology and setup are demonstrated with measurement results from different snapback devices.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134407370","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies 90nm CMOS节点技术中MOSFET ESD击穿触发的先进建模和参数提取
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 1900-01-01 DOI: 10.1109/EOSESD.2004.5272628
V. Vassilev, M. Lorenzini, P. Jansen, G. Groeseneken, S. Thijs, M. Natarajan, M. Steyaert, H. Maes
{"title":"Advanced modelling and parameter extraction of the MOSFET ESD breakdown triggering in the 90nm CMOS node technologies","authors":"V. Vassilev, M. Lorenzini, P. Jansen, G. Groeseneken, S. Thijs, M. Natarajan, M. Steyaert, H. Maes","doi":"10.1109/EOSESD.2004.5272628","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272628","url":null,"abstract":"The electro-static discharge (ESD) breakdown mechanism of 90 nm MOSFET n+/pwell devices is described in detail and modelled with a physics based equation set. The newly developed consistent parameter extraction approach allows to overcome the limitations of existing methodologies, which are not applicable for the 90 nm CMOS node device behaviour, and to calibrate precisely the snapback models. These models will help optimising the ESD robust I/O cells, which use 90 nm MOSFET devices as I/O drivers and ESD structures.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128256513","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions 90nm RF CMOS中5.5 GHz LNA的ESD保护-实现概念、限制和解决方案
2004 Electrical Overstress/Electrostatic Discharge Symposium Pub Date : 1900-01-01 DOI: 10.1109/EOSESD.2004.5272635
S. Thijs, M. Natarajan, D. Linten, V. Vassilev, T. Daenen, A. Scholten, R. Degraeve, P. Wambacq, G. Groeseneken
{"title":"ESD protection for a 5.5 GHz LNA in 90 nm RF CMOS — Implementation concepts, constraints and solutions","authors":"S. Thijs, M. Natarajan, D. Linten, V. Vassilev, T. Daenen, A. Scholten, R. Degraeve, P. Wambacq, G. Groeseneken","doi":"10.1109/EOSESD.2004.5272635","DOIUrl":"https://doi.org/10.1109/EOSESD.2004.5272635","url":null,"abstract":"Design and implementation of ESD protection for a 5.5 GHz Low Noise Amplifier (LNA) fabricated in a 90 nm RF CMOS technology is presented. An on-chip inductor, added as ldquoplug-and-playrdquo, is used as ESD protection for the RF pins. The consequences of design and process, as well as the limited freedom on the ESD protection implementation for all pins to be protected are presented in detail and additional improvements are suggested.","PeriodicalId":302866,"journal":{"name":"2004 Electrical Overstress/Electrostatic Discharge Symposium","volume":"55 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1900-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134171802","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 14
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