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SSIM: A Software Levelized Compiled-Code Simulator SSIM:一个软件级别编译代码模拟器
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37889
L.-T. Wang, N. E. Hoover, Edwin H. Porter, J. Zasio
{"title":"SSIM: A Software Levelized Compiled-Code Simulator","authors":"L.-T. Wang, N. E. Hoover, Edwin H. Porter, J. Zasio","doi":"10.1145/37888.37889","DOIUrl":"https://doi.org/10.1145/37888.37889","url":null,"abstract":"This paper presents a new logic simulation technique that uses software levelized compiled-code (LCC) for synchronous designs. Three approaches are proposed: C source code, target machine code and interpreted code. The evaluation speed for the software LCC simulator (SSIM) is about 140,000 (gate) evaluations per second using C source code or target machine code, or 50,000 evaluations per second using interpreted code. It is about 40 to 100 times slower than the AIDA hardware LCC simulator, but is about one order of magnitude faster than a traditional software event simulator. For a 32-bit multiplier with gate activity more than 100%, experiments indicate that SSIM runs about 250 to 1,000 times faster than the AIDA event simulator that evaluates about 4,500 gates per second.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122663372","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 114
An Overview of Logic Synthesis Systems 逻辑综合系统概述
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37913
L. Trevillyan
{"title":"An Overview of Logic Synthesis Systems","authors":"L. Trevillyan","doi":"10.1145/37888.37913","DOIUrl":"https://doi.org/10.1145/37888.37913","url":null,"abstract":"The term logic synthesis is used to describe systems that range from relatively simple mapping schemes to tools with sophisticated logic optimizations. In this tutorial, the requirements on logic synthesis systems will be discussed aand the advantages and disadvantages of different approaches to logic synthesis will be presented.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"2013 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128008539","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 17
REAL: A Program for REgister ALlocation 一个分配寄存器的程序
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37920
F. Kurdahi, A. C. Parker
{"title":"REAL: A Program for REgister ALlocation","authors":"F. Kurdahi, A. C. Parker","doi":"10.1145/37888.37920","DOIUrl":"https://doi.org/10.1145/37888.37920","url":null,"abstract":"This paper describes the REAL REgister ALlocation program. REAL uses a track assignment algorithm taken from channel routing called the Left Edge algorithm. REAL is optimal for non-pipelined designs with no conditional branches. It is thought that REAL is also optimal for designs with conditional branches, pipelined or not. Experimental results are included in the report, which illustrate the optimal solutions found by REAL. REAL is part of the ADAM Advanced Design AutoMation system, and will be used to process designs output from MAHA and Sehwa.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129930275","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 341
On The Verification of Sequential Machines at Differing Levels of Abstraction 不同抽象层次上顺序机的验证
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37929
S. Devadas, Hi-Keung Tony Ma, A. Newton
{"title":"On The Verification of Sequential Machines at Differing Levels of Abstraction","authors":"S. Devadas, Hi-Keung Tony Ma, A. Newton","doi":"10.1145/37888.37929","DOIUrl":"https://doi.org/10.1145/37888.37929","url":null,"abstract":"In this paper, an algorithm is presented for the verification of the equivalence of two sequential circuit descriptions at the same or differing levels of abstraction, namely at the register-transfer (RT) level and the logic level. The descriptions represent general finite automata at the differing levels -- a finite automaton can be described in a ISP-like language and its equivalence to a logic level implementation can be verified using our algorithm. Two logic level automatons can be similarly verified for equivalence. Previous approaches to sequential circuit verification have been restricted to verifying relatively simple descriptions with small amounts of memory. Unlike these approaches, our technique is shown to be computationally efficient for much more complex circuits. The efficiency of our algorithm lies in the exploitation of don't care information derivable from the RTL or logic level description (e.g invalid input and output sequences) during the verification process. Using efficient cube enumeration procedures at the logic level we have been able to verify the equivalence of finite automata with a large number of states in small amounts of cpu-time.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"233 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127294221","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 87
The Implementation of a State Machine Compiler 状态机编译器的实现
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37978
C. Kingsley
{"title":"The Implementation of a State Machine Compiler","authors":"C. Kingsley","doi":"10.1145/37888.37978","DOIUrl":"https://doi.org/10.1145/37888.37978","url":null,"abstract":"This paper describes VTIstate, VLSI Technology's state machine compiler. The compiler derives combinational logic and registers to make a state machine, and synthesizes the combinational logic with three optimization steps. The 1986 Design Automation conference synthesis benchmark set is used to compare the results with previously reported logic synthesis programs.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126894865","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
PLAY: Pattern-Based Symbolic Cell Layout Part I: Transistor Placement 基于模式的符号单元布局第一部分:晶体管放置
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37994
W.-J. Lue, L. McNamee
{"title":"PLAY: Pattern-Based Symbolic Cell Layout Part I: Transistor Placement","authors":"W.-J. Lue, L. McNamee","doi":"10.1145/37888.37994","DOIUrl":"https://doi.org/10.1145/37888.37994","url":null,"abstract":"This paper describes an approach to symbolic transistor placement from a CMOS circuit net-list as part of an automatic custom cell layout system, PLAY. It consists of two parts, extraction and refinement. The extraction process defines a set of patterns using local connection relationships. Refinement procedures assign topological attributes to each transistor through these patterns and relationships along with other heuristic knowledge. This paradigm provides a new way to embed designers' knowledge for circuit layout. Although only CMOS circuit layout placements are demonstrated, this approach can readily be extended to other technologies. Comparison between PLAY and manual design results is also reported.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"37 8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125734245","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 13
A Fast Signature Simulation Tool for Built-In Self-Testing Circuits 用于内置自检电路的快速签名仿真工具
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37891
S. Tan, K. Totton, K. Baker, P. Varma, R. Porter
{"title":"A Fast Signature Simulation Tool for Built-In Self-Testing Circuits","authors":"S. Tan, K. Totton, K. Baker, P. Varma, R. Porter","doi":"10.1145/37888.37891","DOIUrl":"https://doi.org/10.1145/37888.37891","url":null,"abstract":"This paper describes a Fast Signature Simulator (FSS) tool for Built-In Self-Testing (BIST) circuits. The FSS consists of a simulator generator and a compiled code simulator. The simulator generator comprises a controlling program called the EXECUTIVE and translation software called SIM-GEN. SIM-GEN accepts a Hardware Description Language (HDL) representation of the circuit-under-test as its input and produces C code simulation modules comprising Boolean relations that represent the structure of the circuit. These C code modules are then compiled and linked together to form the basis of the compiled code simulator. Simulation is invoked by executing the compiled C code description of the circuit. The simulation time is minimised by the use of parallel simulation techniques in conjunction with efficient functional models and novel mapping techniques for the LFSRs. Performances approaching 5 Million Gate Evaluations Per Second (GEPS) have been achieved using the FSS.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121509929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
EASE: A Design Support Environment for the HDDL ELLA EASE: HDDL ELLA的设计支持环境
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.38006
J. Morison, N. Peeling, T. L. Thorp, E. Whiting
{"title":"EASE: A Design Support Environment for the HDDL ELLA","authors":"J. Morison, N. Peeling, T. L. Thorp, E. Whiting","doi":"10.1145/37888.38006","DOIUrl":"https://doi.org/10.1145/37888.38006","url":null,"abstract":"This paper describes the ELLA applications support environment - EASE. The support environment allows separate modular compilation and multi-level simulation with almost no semantic or syntatic constructs in the ELLA language. The paper describes the form that the EASE takes and the advantages this gives over other programming support environments. The weaknesses of the current EASE and future work are also discussed.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127884313","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Hardware Accelerator for Maze Routing 一种用于迷宫路由的硬件加速器
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.38014
Y. Won, S. Sahni, Yacoub M. El-Ziq
{"title":"A Hardware Accelerator for Maze Routing","authors":"Y. Won, S. Sahni, Yacoub M. El-Ziq","doi":"10.1145/37888.38014","DOIUrl":"https://doi.org/10.1145/37888.38014","url":null,"abstract":"A hardware accelerator for the maze routing problem is developed. This accelerator consists of three 3 stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"68 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131176044","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
An Automated Design of Minimum-Area IC Power/Ground Nets 最小面积集成电路电源/接地网的自动化设计
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37927
S. Chowdhury
{"title":"An Automated Design of Minimum-Area IC Power/Ground Nets","authors":"S. Chowdhury","doi":"10.1145/37888.37927","DOIUrl":"https://doi.org/10.1145/37888.37927","url":null,"abstract":"Given tree topologies for routing power/ground (p/g) nets in integrated circuits, this paper formulates and solves the problem of determining the widths of the branches of the trees. Constraints are developed in order to maintain proper logic levels and switching speed, to prevent electromigration, and to satisfy certain design rule and regularity requirements. The area required by the p/g distribution system is minimized subject to these constraints. Some case studies are also presented.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132251628","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 27
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