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Circular Self-Test Path: A Low-Cost BIST Technique 圆自测路径:一种低成本的BIST技术
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37949
A. Krasniewski, S. Pilarski
{"title":"Circular Self-Test Path: A Low-Cost BIST Technique","authors":"A. Krasniewski, S. Pilarski","doi":"10.1145/37888.37949","DOIUrl":"https://doi.org/10.1145/37888.37949","url":null,"abstract":"A new technique for designing self-testing VLSI circuits, referred to as Circular Self-Test Path, is presented. The Circular Self-Test Path is a feedback shift register (output of the last flip-flop is supplied to the first flip-flop) with a data compaction capability. A distinguishing attribute of self-testing chips designed using this technique is a low silicon area overhead, slightly exceeding that of scan path designs. A theoretical analysis and comprehensive simulation experiments are performed to demonstrate that the effectiveness of test pattern generation for the circular self-test path is comparable to that of an ideal pseudorandom test generator.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"556 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116445849","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 50
Strip Layout: A New Layout Methodology for Standard Circuit Modules 带状布局:标准电路模块的一种新的布局方法
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37943
J. Apte, G. Kedem
{"title":"Strip Layout: A New Layout Methodology for Standard Circuit Modules","authors":"J. Apte, G. Kedem","doi":"10.1145/37888.37943","DOIUrl":"https://doi.org/10.1145/37888.37943","url":null,"abstract":"In this paper we describe Strip Layout, a new layout methodology that is suitable for automatically laying out standard circuit modules and for automatic module generation from transistor net-list. We demonstrate that the new layout methodology yields circuits that are denser than standard cell layout while retaining all the advantages of standard cells. Moreover, Strip Layout could be generated by simple algorithms at high speed.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129704256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On Computing Optimized Input Probabilities for Random Tests 计算随机测试的优化输入概率
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37947
H. Wunderlich
{"title":"On Computing Optimized Input Probabilities for Random Tests","authors":"H. Wunderlich","doi":"10.1145/37888.37947","DOIUrl":"https://doi.org/10.1145/37888.37947","url":null,"abstract":"Self testing of integrated circuits by random patterns has several technical and economical advantages. But there exists a large number of circuits which cannot be randomly tested, since the fault coverage achieved that way would be too low. In this paper we show that this problem can be solved by unequiprobable random patterns, and an efficient procedure is presented computing the specific optimal probability for each primary input of a combinational network. Those optimized random patterns can be produced on the chip during self test or off the chip in order to accelerate fault simulation and test pattern generation.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129969741","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 52
Application of Term Rewriting Techniques to Hardware Design Verification 术语重写技术在硬件设计验证中的应用
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37930
M. Chandrasekhar, J. Privitera, Kenneth W. Conradt
{"title":"Application of Term Rewriting Techniques to Hardware Design Verification","authors":"M. Chandrasekhar, J. Privitera, Kenneth W. Conradt","doi":"10.1145/37888.37930","DOIUrl":"https://doi.org/10.1145/37888.37930","url":null,"abstract":"Term rewriting systems have been used in automatic theorem proving. A canonical term rewriting system for boolean algebra recently discovered, and a refutation technique using Knuth-Bendix completion procedure can be used to prove boolean formulas arising in logic verification. In this paper a design verification system based on term rewriting techniques is presented. It can prove total correctness of combinational circuits without exhaustive simulation. A prototype system implemented on a Motorola 68010 based workstation shows that the system performs favorably compared to a simulator.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128723929","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 37
ASTA: LSI Design Management System 大规模集成电路设计管理系统
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37967
T. Ogihara, H. Toyoshima, S. Murai
{"title":"ASTA: LSI Design Management System","authors":"T. Ogihara, H. Toyoshima, S. Murai","doi":"10.1145/37888.37967","DOIUrl":"https://doi.org/10.1145/37888.37967","url":null,"abstract":"This paper deals with an LSI design management system which automates CAD program performance analysis. CAD program/library version control, design process control, design cost estimation and the collection of such statistical information as the sizes of the circuits being designed. The design management automation has been accomplished by analyzing statistical and control information generated by all the CAD programs and the operating system.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"35 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129623404","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Improved Systematic Method for Constructing Systolic Arrays from Algorithms 一种基于算法构造收缩数组的改进系统方法
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37892
N. Faroughi, M. Shanblatt
{"title":"An Improved Systematic Method for Constructing Systolic Arrays from Algorithms","authors":"N. Faroughi, M. Shanblatt","doi":"10.1145/37888.37892","DOIUrl":"https://doi.org/10.1145/37888.37892","url":null,"abstract":"An improved systematic method is introduced which reduces the number of ad hoc steps and provides all possible systolic solutions for a given algorithm. Algorithms are modeled using index space (geometric) representations where the index transformation matrices are determined systematically. Systolic arrays are produced by geometric projections.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130423415","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts 半定制集成电路布局预测评估的离散启发式方法
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.38010
A. Minai, Ronald D. Williams, F. W. Blake
{"title":"A Discrete Heuristics Approach to Predictive Evaluation of Semi-Custom IC Layouts","authors":"A. Minai, Ronald D. Williams, F. W. Blake","doi":"10.1145/37888.38010","DOIUrl":"https://doi.org/10.1145/37888.38010","url":null,"abstract":"The significant computational requirements of VLSI layout suggest that it may be desirable to estimate the feasibility of a task before actually performing the task. The system described in this paper uses a discrete heuristics approach to estimate the future quality of a semi-custom layout before any placement or routing is done. It does this evaluation with respect to critical parameters such as routability, area utilization, and wire length, using heuristics arranged in a discrete graph structure. The system can handle user-specified non-rectangular layout shapes. Its rule-based structure allows easy observation and modification of individual heuristics for the purposes of \"fine tuning.\" The system also detects potential problems and suggests possible solutions.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"8 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122144701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Layout Optimization of CMOS Functional Cells CMOS功能单元布局优化
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37969
R. L. Maiasz, J. Hayes
{"title":"Layout Optimization of CMOS Functional Cells","authors":"R. L. Maiasz, J. Hayes","doi":"10.1145/37888.37969","DOIUrl":"https://doi.org/10.1145/37888.37969","url":null,"abstract":"An optimal non-exhaustive method of minimizing the layout area of complementary series-parallel CMOS functional cells in the standard-cell style is presented. This generalizes earlier work of Uehara and vanCleemput which is heuristic and nonoptimal. A complete graph-theoretical framework for CMOS cell layout is developed and illustrated. The approach demonstrates a new class of graph-based algebras which characterize this layout problem.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"52 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115044249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 53
LCS-A Leaf Cell Synthesizer Employing Formal Deduction Techniques LCS-A叶细胞合成器采用形式演绎技术
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37956
P. Subrahmanyam
{"title":"LCS-A Leaf Cell Synthesizer Employing Formal Deduction Techniques","authors":"P. Subrahmanyam","doi":"10.1145/37888.37956","DOIUrl":"https://doi.org/10.1145/37888.37956","url":null,"abstract":"This paper discusses the use of formal reasoning techniques to aid in the automated structural design of leaf cells, in the more global context of VLSI circuit design. The technique supports an encapsulation of the technology-dependent aspects of a design by using appropriate formal models, and guarantees the consistency of the designs produced with respect to the functional specification and the technology model employed. The approach is illustrated by its use in the design of some leaf cells in CMOS. The role of the techniques when used in an interactive mode and in the verification of existing designs is also discussed.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"64 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132480139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Application of Exploratory Data Analysis Techniques to Floorplan Design 探索性数据分析技术在平面图设计中的应用
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37993
E. Kouka, G. Saucier
{"title":"An Application of Exploratory Data Analysis Techniques to Floorplan Design","authors":"E. Kouka, G. Saucier","doi":"10.1145/37888.37993","DOIUrl":"https://doi.org/10.1145/37888.37993","url":null,"abstract":"This paper presents an advisory tool for fast cost estimation of floorplans made up of rectangular arbitrarily-sized building blocks. Emphasis is laid on efficient computer processing of available data. The floorplan information is translated into proximity matrices. Exploratory data analysis, based on a multivariate statistical approach, is used with a view to revealing patterns inherent in the data. The resultant patterns are then converted into metric representations.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"39 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123351809","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
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