Layout Optimization of CMOS Functional Cells

Abstract

An optimal non-exhaustive method of minimizing the layout area of complementary series-parallel CMOS functional cells in the standard-cell style is presented. This generalizes earlier work of Uehara and vanCleemput which is heuristic and nonoptimal. A complete graph-theoretical framework for CMOS cell layout is developed and illustrated. The approach demonstrates a new class of graph-based algebras which characterize this layout problem.