{"title":"An Interface between VHDL and EDIF","authors":"M. Shahdad","doi":"10.1145/37888.37958","DOIUrl":"https://doi.org/10.1145/37888.37958","url":null,"abstract":"The VHSIC Hardware Description Language (VHDL) and the Electronic Design Interchange Format (EDIF) are becoming industry standards for hardware design and documentation. Potential users of these standards are interested in understanding the application range of each standard and the way each standard relates to the other. This paper presents scenarios in which VHDL and EDIF can contribute to different aspects of the design process, as well as the technical issues in providing a design interface between VHDL and EDIF. Both standards are currently being reviewed and revised [1] [2]. In this paper we have used VHDL Version 1076/A [3] and EDIF Version 1 1 0 [4].","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"30 5","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120866425","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Expert System Application in Semicustom VLSI Design","authors":"R. Steele","doi":"10.1145/37888.37997","DOIUrl":"https://doi.org/10.1145/37888.37997","url":null,"abstract":"This paper describes the implementation of a prototype expert system that provides standard cell design advice in the areas of performance, manufacturability, testability, and overall design quality, from a netlist description of an application specific integrated circuit (ASIC) design. The system is currently being developed on a Symbolics Lisp Machine using a hybrid AI programming language, called Proteus. The language integrates both known and novel AI programming techniques into a robust vehicle for the implementation of knowledge-based systems. Knowledge representation schemes, inference mechanisms, and knowledge acquisition techniques will be presented, including representative examples from within the knowledge base.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"128 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127083249","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Parts Selection Expert System to Increase Manufacturability","authors":"D. Praizler, G. Fritz","doi":"10.1145/37888.38001","DOIUrl":"https://doi.org/10.1145/37888.38001","url":null,"abstract":"This paper describes the Parts Selection Advisor, a prototype expert system applied to component selection. The Parts Selection Advisor (PSA) condenses the diffuse knowledge of several manufacturing experts into a system that design engineers can use. By leveraging this store of manufacturing knowledge, an engineer can produce a product that will be more economical to manufacture. Manufacturing costs are reduced because the PSA helps the engineer select parts which fit the manufacturing process. In addition, the parts chosen are reliable components from preferred suppliers. This paper also addresses practical issues of expert system construction.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"354 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122762476","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Hierarchical Approach to Test Vector Generation","authors":"S. Chandra, J. Patel","doi":"10.1145/37888.37962","DOIUrl":"https://doi.org/10.1145/37888.37962","url":null,"abstract":"Given a combinational network and a specific stuck-at fault to be detected, there are several approaches to generating a test vector. However, most of these approaches fail to exploit the hierarchy inherent in any complex digital design. This paper presents a hierarchical approach to test vector generation. HIPODEM: A test generation system based on this approach is presented. General procedures to perform forward implication and backtracing in a hierarchical framework are discussed in detail. Experimental results obtained from test runs on both flat-level and hierarchical circuits are compared. For the circuits tried, generating tests from a hierarchical description proved to be faster than doing it from a flat level description of the circuit.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128250935","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Topological Search Algorithm for ATPG","authors":"Tom E. Kirkland, M. R. Mercer","doi":"10.1145/37888.37963","DOIUrl":"https://doi.org/10.1145/37888.37963","url":null,"abstract":"The automatic generation of tests for combinational digital circuits is examined from the standpoint of a guided search through a search space. The limitations of this process, namely the size of the search space and the overall strategy, are identified and methods are presented to reduce the size of the search space as well as produce a more optimal ordering of node assignments. A new algorithm is proposed that uses the smaller search space and the improved ordering for node assignments based on a topological analysis of the circuit. Results are presented indicating that this new algorithm, termed TOPological Search (TOPS), is faster than existing algorithms and also rapidly identifies many redundant faults without search.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"27 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129925327","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
S. Heiler, U. Dayal, Jack A. Orenstein, S. Radke-Sproull
{"title":"An Object-Oriented Approach to Data Management: Why Design Databases Need It","authors":"S. Heiler, U. Dayal, Jack A. Orenstein, S. Radke-Sproull","doi":"10.1145/37888.37939","DOIUrl":"https://doi.org/10.1145/37888.37939","url":null,"abstract":"An object-oriented approach to management of engineering design data requires object persistence, object-specific rules for concurrency control and recovery, views, complex objects and derived data, and specialized treatment of operations, constraints, relationships and type descriptions. We discuss object-orientation as more than an implementation paradigm, and show how an object-oriented approach simplifies both use and implementation of engineering design systems.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131570866","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Force-Directed Scheduling in Automatic Data Path Synthesis","authors":"P. Paulin, J. Knight","doi":"10.1145/37888.37918","DOIUrl":"https://doi.org/10.1145/37888.37918","url":null,"abstract":"The HAL system performs data path synthesis using a new scheduling algorithm that is part of an interdependent scheduling and allocation scheme. This scheme uses an estimate of the hardware allocation to guide and optimize the scheduling subtask. The allocation information includes the number, type, speed and cost of hardware modules as well as the associated multiplexer and interconnect costs. The iterative force-directed scheduling algorithm attempts to balance the distribution of operations that make use of the same hardware resources: * Every feasible control step assignment is evaluated at each iteration, for all operations. * The associated side-effects on all the predecessor and successor operations are taken into account. * All the decisions are global. * The algorithm has O(n/sup2/) complexity. We review and compare existing scheduling techniques. Moderate and difficult examples are used to illustrate the effectiveness of the approach.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"139 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"124400608","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Realistic Fault Modeling for VLSI Testing","authors":"Wojciech Maly","doi":"10.1145/37888.37914","DOIUrl":"https://doi.org/10.1145/37888.37914","url":null,"abstract":"Functional failures of VLSI circuits are caused by process-induced defects. Such defects have very complex physical characteristics and may be significantly different from the simplistic defect models assumed by typical fault modeling techniques. In the tutorial an overview of the actual mechanisms causing processing defects, and the defects' electrical manifestations will be discussed. It will be demonstrated that inadequate insight into the physics of processing defects and the manufacturing process may lead to inefficient testing of actual VLSI circuits.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125870329","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Hardware Switch Level Simulator for Large MOS Circuits","authors":"M. Smith","doi":"10.1145/37888.37902","DOIUrl":"https://doi.org/10.1145/37888.37902","url":null,"abstract":"The HSS is a Hardware Switch level Simulator that has been designed and built to be a useful and cost effective addition to a MOS circuit designers tool set. The HSS is based on the MOSSIM software simulator, but has been further developed to include hardware for simulating pass transistor circuits and for doing timing simulation. By using dynamic RAM for internal list storage, a single HSS processor can accommodate a circuit of up to 262,144 MOS devices. The HSS can be interfaced to a variety of host computers via a general purpose parallel interface, and in its current form offers a 25 times speed improvement compared to MOSSIM II running on a VAX 11-780. Timing mode offers similar speed advantages, with delay calculations that are sufficiently accurate for many simulation tasks.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130144431","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Optimal Layout to Avoid CMOS Stuck-Open Faults","authors":"S. Koeppe","doi":"10.1145/37888.37998","DOIUrl":"https://doi.org/10.1145/37888.37998","url":null,"abstract":"A set of layout rules is presented to cope with CMOS stuck-open faults by a design for testability at the layout-level. In applying these rules, open connections may either be avoided or their effects can be described by an easily detectable type of open faults known from CMOS inverters and NMOS logic. Hence, remaining open faults are usually covered by a complete stuck-at test pattern set.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132389467","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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