Optimal Layout to Avoid CMOS Stuck-Open Faults

Abstract

A set of layout rules is presented to cope with CMOS stuck-open faults by a design for testability at the layout-level. In applying these rules, open connections may either be avoided or their effects can be described by an easily detectable type of open faults known from CMOS inverters and NMOS logic. Hence, remaining open faults are usually covered by a complete stuck-at test pattern set.