{"title":"Functional Abstraction from Structure in VLSI Simulation Models","authors":"R. Lathrop, R. Hall, R. Kirk","doi":"10.1145/37888.37916","DOIUrl":"https://doi.org/10.1145/37888.37916","url":null,"abstract":"High-level functional (or behavioral) simulation models are difficult, time-consuming, and expensive to develop. We report on a method for automatically generating the program code for a high-level functional simulation model. The high-level model is produced directly from the program code for the circuit components' functional models and a netlist description of their connectivity. A prototype has been implemented in LISP for the SIMMER functional simulator.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"37 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132164391","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Hi-Keung Tony Ma, S. Devadas, Ruey-Sing Wei, A. Sangiovanni-Vincentelli
{"title":"Logic Verification Algorithms and their Parallel Implementation","authors":"Hi-Keung Tony Ma, S. Devadas, Ruey-Sing Wei, A. Sangiovanni-Vincentelli","doi":"10.1145/37888.37931","DOIUrl":"https://doi.org/10.1145/37888.37931","url":null,"abstract":"LOVER incorporates a novel approach to combinational logic verification and obtains good results when compared to existing techniques. In this paper we describe a new verification algorithm, LOVER-PODEM, whose enumeration phase is based on PODEM. A variant of LOVER-PODEM, called PLOVER, is presented. We have developed, for the first time, parallel logic verification schemes. Issues in efficiently parallelizing both general and specific LOVER-based approaches to logic verification over a large number of processors are addressed. We discuss parallelism inherent in the LOVER framework regardless of what enumeration and simulation algorithms are used. Since the enumeration phase is the efficiency bottleneck in parallelizing LOVER-based approaches, we have developed parallel versions of PODEM-based enumeration algorithms. Experimental results are presented to show that high processor utilization can be achieved when these parallelisms are exploited. Speed-up factors of over 7.8 have been achieved with 8 processor configurations.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130279216","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"On Yield Consideration for the Design of Redundant Programmable Logic Arrays","authors":"C. Wey","doi":"10.1145/37888.37986","DOIUrl":"https://doi.org/10.1145/37888.37986","url":null,"abstract":"This paper presents the design of a programmable logic array with redundancy. The design allows for the repair of a defective chip by including the redundancy circuits to a conventional PLA. When the redundancy technique is implemented into the VLSI or WSI chip design, the increased cost is proportional to the increased chip silicon area. Indeed, the additional spare lines may increase the silicon area and propagation delay. However, if the provided redundancy can be efficiently utilized to repair the defective chip, then the additional spare lines may increase rather decrease the chip yields. The objective of the present paper is to analyze the possibility of yield enhancement rhrough redundant design.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"80 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127857958","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Improving Virtual-Grid Compaction Through Grouping","authors":"Liars S. Nylund, S. Daniel, Lb-ward Rogers","doi":"10.1145/37888.37934","DOIUrl":"https://doi.org/10.1145/37888.37934","url":null,"abstract":"In the past, Virtual-Grid Compactors have not been well received because they generated sparse layouts. In analyzing this problem, we found three major areas where improvements could be made: breaking the virtual-grid lines into segments; decoupling the placement of non-interacting layers; and eliminating the centered nature of elements. The result is a compactor with substantially better mask generation.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126723520","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PHRAN-SPAN: A Natural Language Interface for System Specifications","authors":"J. Granacki, A. C. Parker","doi":"10.1145/37888.37950","DOIUrl":"https://doi.org/10.1145/37888.37950","url":null,"abstract":"This paper describes a natural language interface, PHRAN-SPAN, for specifying the abstract behavior of digital systems in restricted English text. A neutral formal representation for the behavior is described using the USC Design Data Structure. A small set of concepts that characterize digital system behavior are presented using this representation. Finally, an intermediate representation based on Conceptual Dependencies is presented. Its use with a semantic-based parser to translate from English to the formal representation is illustrated by a series of examples.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":" 17","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"113949435","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Path Selection Global Router","authors":"Y. Hsu, Y. Pan, W. Kubitz","doi":"10.1145/37888.37990","DOIUrl":"https://doi.org/10.1145/37888.37990","url":null,"abstract":"In this paper, a new path selection heuristic search algorithm is proposed for connecting two components of vertices. A novel feature of the algorithm is that the active terminals (vertices in the net which are not yet connected) are modeled as magnets during the path searching process. The heuristic search algorithm is applied to two commonly used multi-terminal net tree connection algorithms. Experimental results show that the new path selection heuristic search algorithm is better than the other algorithms which do not consider the active terminals.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121279623","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"PALMINI-Fast Boolean Minimizer for Personal Computer","authors":"L. Nguyen, M. A. Perkowdki, N. B. Goldstein","doi":"10.1145/37888.37985","DOIUrl":"https://doi.org/10.1145/37888.37985","url":null,"abstract":"This paper describes a fast and efficient method for minimization of two level single output Boolean functions. The minimization problem is reduced to that of coloring of the graph of incompatibility of implicants. The program permits also to remove static hazards and allows inversion of output's polarity which proves to be very convenient when designing with PAL's. It gives solutions within a very reasonable amount of time. On small industrial examples its speed is slightly better than Espresso and it occupies 6 times less memory.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134068256","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Aesop: A Tool for Automated Transistor Sizing","authors":"Kye S. Hedlund","doi":"10.1145/37888.37905","DOIUrl":"https://doi.org/10.1145/37888.37905","url":null,"abstract":"This work addresses the problem of automating the electrical optimization of combinatorial MOS circuits. Improvements to a circuit's speed, area and power consumption are sought through modifications to the transistor sizes in the circuit; no changes in the circuit structure, number of gates or clocking are introduced. Linear algorithms are presented for computing optimal transistor sizes to minimize delay, area or power. These algorithms are implemented in an interactive tool, Aesop. Aesop is a powerful and fast \"what-if\" tool that allows the designer to explore the space of designs having optimal transistor sizes. When compared to manual designs, the circuits produced by Aesop are typically faster or have substantially lower area and power consumption. Compared to untuned circuits, Aesop typically increases circuit speed by a factor of 2 to 4. Alternatively, power consumption and transistor area can be reduced by 25 -- 50% with no sacrifice in circuit speed. These improvements are computed interactively on a professional workstation for circuits containing thousands of transistors.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"127 9","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114025090","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Automated Layout Generation Using Gate Matrix Approach","authors":"Y.-C. Chang, S. Chang, L.-H. Hsu","doi":"10.1145/37888.37970","DOIUrl":"https://doi.org/10.1145/37888.37970","url":null,"abstract":"This paper presents a software system ALS-UGMA for automated gate matrix layout generation. Its structured Net-List and Realization Matrix models which are different from previous interval graph approach are introduced. Algorithms to minimize and realize the gate matrix layout are also presented with examples. Empirical results showed good performance in terms of both speed and layout quality. Folding technique for such layout style is also introduced.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115099220","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Dynamic Programming Approach to the Test Point Insertion Problem","authors":"B. Krishnamurthy","doi":"10.1145/37888.38000","DOIUrl":"https://doi.org/10.1145/37888.38000","url":null,"abstract":"The test point insertion problem is that of selecting t nodes in a combinational network as candidates for inserting observable test points, so as to minimize the number of test vectors needed to detect all single stuck-at faults in the network. In this paper we describe a dynamic programming approach to selecting the test points and provide an algorithm that inserts the test points optimally for fanout-free networks. We further extend this algorithm to general combinational networks with reconvergent fanout. We also analyze the time complexity of the algorithm and show that it runs in O(n-t) time, where n is the size of the network and t is the number of test points to be inserted. As a side result we show that we can compute minimal test sets for a restricted class of networks that includes fanout. This extends previous results which were limited to fanout-free networks.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"44 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123133895","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
求助内容：
应助结果提醒方式：
京公网安备 11010802042870号
