An Interface between VHDL and EDIF

Abstract

The VHSIC Hardware Description Language (VHDL) and the Electronic Design Interchange Format (EDIF) are becoming industry standards for hardware design and documentation. Potential users of these standards are interested in understanding the application range of each standard and the way each standard relates to the other. This paper presents scenarios in which VHDL and EDIF can contribute to different aspects of the design process, as well as the technical issues in providing a design interface between VHDL and EDIF. Both standards are currently being reviewed and revised [1] [2]. In this paper we have used VHDL Version 1076/A [3] and EDIF Version 1 1 0 [4].