Realistic Fault Modeling for VLSI Testing

Abstract

Functional failures of VLSI circuits are caused by process-induced defects. Such defects have very complex physical characteristics and may be significantly different from the simplistic defect models assumed by typical fault modeling techniques. In the tutorial an overview of the actual mechanisms causing processing defects, and the defects' electrical manifestations will be discussed. It will be demonstrated that inadequate insight into the physics of processing defects and the manufacturing process may lead to inefficient testing of actual VLSI circuits.