{"title":"BIST-PLA: A Built-In Self-Test Design of Large Programmable Logic Arrays","authors":"Chun-Yeh Liu, K. Saluja, S. Upadhyaya","doi":"10.1145/37888.37946","DOIUrl":"https://doi.org/10.1145/37888.37946","url":null,"abstract":"A new method for designing a Built-In Self-Test Programmable Logic Array (BIST-PLA) is presented. In the proposed design, the Test Pattern Generator and the Response Evaluator circuits are very simple. The design requires a rearrangement of the AND (OR) planes on the basis of number of crosspoints in the product (output) lines in the PLA. The BIST-PLA proposed in this paper is capable of detecting all single stuck-at and crosspoint faults and almost all multiple faults, thus offering fault coverage higher than any of the known BIST designs of PLAs. A program has been written which generates a BIST-PLA. The program was used to study 22 large PLAs from the list of 56 PLAs given in [18]. It was found that the silicon area overhead for almost all these PLAs was lower than those using methods reported in literature [10] [11] [12] [13] [14] [15] [16] [17]. Furthermore, the delay performance degradation was found to be within acceptable limits. The program was developed in the unix environment (4.3beta BSD UNIX) and is integratable with the existing design automation tools.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129511107","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"LES: A Layout Expert System","authors":"Y. Lin, D. Gajski","doi":"10.1145/37888.37996","DOIUrl":"https://doi.org/10.1145/37888.37996","url":null,"abstract":"In this paper we describe an expert system for layout generation in a hierarchical VLSI design system. It applies a combination of rule- and algorithmic-based techniques on a new layout style. Experimental results have demonstrated the superiority of this expert system against various standard-cell systems and its competitiveness with human designers.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"23 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129415830","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Fast Printed Circuit Board Routing","authors":"Jeremy Dion","doi":"10.1145/37888.38004","DOIUrl":"https://doi.org/10.1145/37888.38004","url":null,"abstract":"This paper describes the algorithms in a printed circuit board router used for fully automatic routing of high-density circuit boards. Completely automatic routing and running times of a few minutes have resulted from a new data structure for efficient representation of the routing grid, quick searches for optimal solutions, and generalizations of Lee's algorithm.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"69 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133533084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Rationale for and Organization of the Engineering Information System Program","authors":"A. Gadient, J. Ebel","doi":"10.1145/37888.38009","DOIUrl":"https://doi.org/10.1145/37888.38009","url":null,"abstract":"The need for a robust, multi-user, integrated design environment for electronic systems is the result of the phenomenal growth in integrated circuit fabrication technology over the last decade. Attempts to develop \"integrated\" design environments highlight the current lack in design tool interoperability. The Very High Speed Integrated Circuits (VHSIC) program recognizes the importance of integrated design environments for the design of future defense electronic systems and for the insertion of new technologies into existing electronic systems, and is attempting to ease the task of integrating disparate electronic system design aids by addressing the design tool interoperability problem through the Engineering Information System (EIS) program. This paper describes the rationale for the EIS program, highlights its goals, and outlines the program's structure.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"75 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131407731","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"REDS: Resistance Extraction for Digital Simulation","authors":"D. Stark, M. Horowitz","doi":"10.1145/37888.37976","DOIUrl":"https://doi.org/10.1145/37888.37976","url":null,"abstract":"This paper describes an extractor designed to produce resistance values for use in digital circuit simulation. REDS avoids resistance extraction on most nets in a design using a simple filter based on the perimeter and area values calculated by the capacitance extractor, allowing it to concentrate on areas where resistance may substantially affect circuit timing. Nets are extracted using a fast square counting algorithm, and simplified before output to remove spurious elements. REDS is designed to work on the Magic layout database.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131338203","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Where VHDL Fits within the CAD Environment","authors":"J. Hines","doi":"10.1145/37888.37961","DOIUrl":"https://doi.org/10.1145/37888.37961","url":null,"abstract":"This paper discusses the relationship of the VHSIC Hardware Description Language (VHDL), the Electronic Design Interchange Format (EDIF), and the Initial Graphics Exchange Specification (IGES) in a Computer Aided Design (CAD) environment.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129715387","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Mesh Arrays and Logician: A Tool for Their Efficient Generation","authors":"Jared A. Beekman, R. Owens, M. J. Irwin","doi":"10.1145/37888.37942","DOIUrl":"https://doi.org/10.1145/37888.37942","url":null,"abstract":"This paper introduces a standard structure for VLSI design which we call the mesh array and describes a design tool called LOGICIAN which minimizes a set of functions for realization in CMOS mesh arrays. LOGICIAN features multi-level logic synthesis through recursive enumeration of each function. Several techniques to speed-up the minimization process in LOGICIAN are described.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"16 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130045706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A High Performance Routing Engine","authors":"T. D. Spiers, D. Edwards","doi":"10.1145/37888.38013","DOIUrl":"https://doi.org/10.1145/37888.38013","url":null,"abstract":"A hardware architecture for implementing Lee based routing algorithms is described. The design features hardware implementations of the main data structures and parallelism among a number of specialised processing elements. An engine based on this architecture has been constructed which executes a sophisticated cost-based algorithm 40 times faster than a VAX 11/780.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131163277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Louis-Philippe Demers, P. Jacques, S. Fauvel, E. Cerny
{"title":"CHESHIRE: An Object-Oriented Integration of VLSI CAD Tools","authors":"Louis-Philippe Demers, P. Jacques, S. Fauvel, E. Cerny","doi":"10.1145/37888.38007","DOIUrl":"https://doi.org/10.1145/37888.38007","url":null,"abstract":"We present an approach to the integration of VLSI CAD tools through the uniformization of interactions with design cells at both the user and the program levels. The integration model is based on the concept of objects applied to circuit cells. User interactions are achieved through a desk-top-like graphics interface. Regrouping of related or equivalent cell-objects into tissues represented by a generic cell helps with their management. Late binding of specific version cells then encourages exploration of the design space. To test the integration concept, a data base and tools for symbolic layout were developed.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"137 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132376363","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Standard Cell Placement Using Simulated Sintering","authors":"Lov K. Grover","doi":"10.1145/37888.37896","DOIUrl":"https://doi.org/10.1145/37888.37896","url":null,"abstract":"Simulated annealing is a powerful optimization technique based on the annealing phenomenon in crystallization. In this paper we propose a simulated sintering technique which is analogous to the sintering process in material processing. In sintering one improves the quality of a processed material by heating it to a temperature close to the melting point. Analogously, we show that by starting out with a good initial configuration instead of a random configuration, and restricting uphill moves, we can considerably speed up simulated annealing. We use this idea for a standard cell placement program - GRIM in LTX2, an AT&T Bell Labs VLSI layout system. The initial configuration is produced either by changes to a layout the designer had done previously, or else by a fast program like min-cut. We obtain improvements of about 10% in chip area starting from a min-cut placement, in times about 3 times faster than our simulated annealing program (which itself is several times faster than other well known simulated annealing programs).","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"56 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122365694","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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