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Routing with a Scanning Window - A Unified Approach 带扫描窗口的路由——一种统一的方法
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37987
David Kaplan
{"title":"Routing with a Scanning Window - A Unified Approach","authors":"David Kaplan","doi":"10.1145/37888.37987","DOIUrl":"https://doi.org/10.1145/37888.37987","url":null,"abstract":"A general approach to routing by a scanning window is presented, and an experimental switch-box router based on this approach is described. This router first grades conductor segments that are candidates to enter the window according to their estimated contributions to routing success, and then uses a quasi-maximal set of segments. A grade function that imitates human intuition is also described.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"146 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132971274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Nutcracker: An Efficient and Intelligent Channel Spacer 胡桃夹子:一个高效和智能的通道间隔器
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37933
X. Xiong, E. Kuh
{"title":"Nutcracker: An Efficient and Intelligent Channel Spacer","authors":"X. Xiong, E. Kuh","doi":"10.1145/37888.37933","DOIUrl":"https://doi.org/10.1145/37888.37933","url":null,"abstract":"A new algorithm for channel spacing is discussed in this paper. In contrast to existing compaction algorithms, we rely on the geometric method and bypass the constraint graph during the whole spacing process. We propose an efficient way to enumerate all possible jogs. Therefore, for the given channel routing topology, our algorithm yields the minimal channel height with the incorporation of contacts sliding and automatic jog insertion. In the final output, only necessary jogs are inserted, and the total wire length is minimized.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"9 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125617019","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
CASE: An Integrated Design Environment for Algorithm-Driven Architectures 案例:算法驱动架构的集成设计环境
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37982
D. Bulterman
{"title":"CASE: An Integrated Design Environment for Algorithm-Driven Architectures","authors":"D. Bulterman","doi":"10.1145/37888.37982","DOIUrl":"https://doi.org/10.1145/37888.37982","url":null,"abstract":"One use of integrated System-level Design Automation (SLDA) tools is during the development of algorithm-driven architectures. In this paper, we discuss an approach to structuring SLDA tools that provides application-area designers a flexible range of support for migrating algorithms into special-purpose computer networks. Using digital signal processing applications as an example problem domain, we discuss the motivation and current implementation of a set of design migration tools used to develop real-time distributed architectures as part of the Brown Computer-Aided System Engineering (CASE) project.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"29 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125094659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Knowledge-Based Approach for the Verification of CAD Database Generated by an Automatic Schematic Capture System 基于知识的原理图自动采集系统CAD数据库验证方法
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.38002
J. Tou, W. H. Ki, K. Fan, C. L. Huang
{"title":"Knowledge-Based Approach for the Verification of CAD Database Generated by an Automatic Schematic Capture System","authors":"J. Tou, W. H. Ki, K. Fan, C. L. Huang","doi":"10.1145/37888.38002","DOIUrl":"https://doi.org/10.1145/37888.38002","url":null,"abstract":"CAD database generated by an automatic schematic capture system needs to be verified before it can be used in design automation. This verification is best performed by a knowledge-based expert system. Presented in this paper is the design of a knowledge-based system for the verification of CAD database generated by AUTORED. Database-driven, pattern-directed inference technique is employed to identify and correct erroneous data records due to misrecognition. This knowledge-based verification system has been implemented on a VAX 11/750 equipped with a video camera to read circuit diagrams into the computer. Integration of this verification system into AUTORED makes the automatically generated database accurate for design automation applications.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"96 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123946636","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic 分析高速信号作为时钟逻辑时序延迟的反射
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37908
R. E. Canright, A. Helland
{"title":"Reflections of High Speed Signals Analyzed as a Delay in Timing for Clocked Logic","authors":"R. E. Canright, A. Helland","doi":"10.1145/37888.37908","DOIUrl":"https://doi.org/10.1145/37888.37908","url":null,"abstract":"This paper develops equations that can extend the performance of high speed digital systems. The equations allow the application of timing analysis to the selection of the minimum series terminating resistor. Use of the minimum terminating resistor minimizes power dissipation and maximizes the drive capability of the terminated device. Detailed examples simplify the adaptation of these new design procedures to computer-aided design (CAD).","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"5 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121309782","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
An Intelligent Compiler SubSystem for a Silicon Compiler 硅编译器的智能编译子系统
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37954
D. Johannsen, S. Tsubota, K. McElvain
{"title":"An Intelligent Compiler SubSystem for a Silicon Compiler","authors":"D. Johannsen, S. Tsubota, K. McElvain","doi":"10.1145/37888.37954","DOIUrl":"https://doi.org/10.1145/37888.37954","url":null,"abstract":"This paper presents a module generator which automatically generates and optimizes circuitry to satisfy constraints of speed, area and power. The user has complete control over the clock timing driving the circuitry and the area, width, or height of the resulting module. Unlike other programs that have benn optimized for area and speed, this program supports more degrees of freedom and a broad range of circuit constructs, permitting a complete integrated circuit to be designed to meet the overall IC project objectives.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"247 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116425345","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Fast, Small, and Static Combinatorial CMOS Circuits 快速，小型，静态组合CMOS电路
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37955
B. Serlet
{"title":"Fast, Small, and Static Combinatorial CMOS Circuits","authors":"B. Serlet","doi":"10.1145/37888.37955","DOIUrl":"https://doi.org/10.1145/37888.37955","url":null,"abstract":"We present ALPS, a new way to generate layout from boolean equations. We use an original tree-structured representation of arbitrary boolean expressions, more compact than classic disjunctive form, allowing fast symbolic manipulation and natural mapping onto silicon. This implementation of ALPS produces static CMOS layout using a cascode-switch style. We present measurements done on fabricated circuits. For a large class of functions, particularly semi-regular control logic, VLSI layout generated by ALPS compares favorably in speed and area to PLAS and Standard-Cell designs.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"38 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"120993053","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator 以硅编译软件工程为例，HVDEV高压器件布局发生器
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37900
N. Elias
{"title":"A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator","authors":"N. Elias","doi":"10.1145/37888.37900","DOIUrl":"https://doi.org/10.1145/37888.37900","url":null,"abstract":"Philips Laboratories has developed HVDEV, a procedural language layout generator for compiling high voltage MOS device layouts from behavioral specifications. HVDEV is analyzed as a case study in silicon compilation software engineering. The paper formulates a comparative analysis to conventional layout design accounting for software development and maintenance. Critical factors in planning silicon compilation software development are identified.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"92 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121073967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
The IBM VHDL Design System IBM VHDL设计系统
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37960
L. Saunders
{"title":"The IBM VHDL Design System","authors":"L. Saunders","doi":"10.1145/37888.37960","DOIUrl":"https://doi.org/10.1145/37888.37960","url":null,"abstract":"This paper presents the IBM VHDL Design System. This set of Computer Aided Engineering (CAE) design tools, built around the VHSIC Hardware Description Language (VHDL) and developed for IBM internal use, along with other design automation tools, is used by IBM design engineers to develop computer hardware. The function and operation of each piece of the system is described. IBM usage and some of the problems encountered are also discussed.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121427439","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 28
On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates 复杂栅极桥接故障的开关级建模精度研究
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37924
R. Rajsuman, Y. Malaiya, A. Jayasumana
{"title":"On Accuracy of Switch-Level Modeling of Bridging Faults in Complex Gates","authors":"R. Rajsuman, Y. Malaiya, A. Jayasumana","doi":"10.1145/37888.37924","DOIUrl":"https://doi.org/10.1145/37888.37924","url":null,"abstract":"Bridging faults have been shown to be a major failure mode in VLSI devices. This study examines nMOS and CMOS complex gates in detail for bridging faults. Analysis is carried out using both switch and circuit level models for comparison. It is shown that in most cases, the switch level analysis predicts the correct behavior. A set of conditions are presented, under which the switch level analysis may fail to predict the correct behavior. These conditions can be used for accurate switch level test generation and simulation.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121804891","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 39
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