BIST-PLA: A Built-In Self-Test Design of Large Programmable Logic Arrays

Abstract

A new method for designing a Built-In Self-Test Programmable Logic Array (BIST-PLA) is presented. In the proposed design, the Test Pattern Generator and the Response Evaluator circuits are very simple. The design requires a rearrangement of the AND (OR) planes on the basis of number of crosspoints in the product (output) lines in the PLA. The BIST-PLA proposed in this paper is capable of detecting all single stuck-at and crosspoint faults and almost all multiple faults, thus offering fault coverage higher than any of the known BIST designs of PLAs. A program has been written which generates a BIST-PLA. The program was used to study 22 large PLAs from the list of 56 PLAs given in [18]. It was found that the silicon area overhead for almost all these PLAs was lower than those using methods reported in literature [10] [11] [12] [13] [14] [15] [16] [17]. Furthermore, the delay performance degradation was found to be within acceptable limits. The program was developed in the unix environment (4.3beta BSD UNIX) and is integratable with the existing design automation tools.