Standard Cell Placement Using Simulated Sintering

Abstract

Simulated annealing is a powerful optimization technique based on the annealing phenomenon in crystallization. In this paper we propose a simulated sintering technique which is analogous to the sintering process in material processing. In sintering one improves the quality of a processed material by heating it to a temperature close to the melting point. Analogously, we show that by starting out with a good initial configuration instead of a random configuration, and restricting uphill moves, we can considerably speed up simulated annealing. We use this idea for a standard cell placement program - GRIM in LTX2, an AT&T Bell Labs VLSI layout system. The initial configuration is produced either by changes to a layout the designer had done previously, or else by a fast program like min-cut. We obtain improvements of about 10% in chip area starting from a min-cut placement, in times about 3 times faster than our simulated annealing program (which itself is several times faster than other well known simulated annealing programs).