CMOS功能单元布局优化

24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI:10.1145/37888.37969

R. L. Maiasz, J. Hayes

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引用次数: 53

摘要

提出了一种使互补串并联CMOS功能单元布局面积最小的非穷穷优化方法。这概括了Uehara和vanCleemput早期的启发式和非最优的工作。开发并说明了CMOS单元布局的完整图理论框架。该方法展示了一类新的基于图的代数，它表征了这个布局问题。

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Layout Optimization of CMOS Functional Cells

An optimal non-exhaustive method of minimizing the layout area of complementary series-parallel CMOS functional cells in the standard-cell style is presented. This generalizes earlier work of Uehara and vanCleemput which is heuristic and nonoptimal. A complete graph-theoretical framework for CMOS cell layout is developed and illustrated. The approach demonstrates a new class of graph-based algebras which characterize this layout problem.

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来源期刊

24th ACM/IEEE Design Automation Conference

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