A Hardware Accelerator for Maze Routing

24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI:10.1145/37888.38014

Y. Won, S. Sahni, Yacoub M. El-Ziq

引用次数: 24

Abstract

A hardware accelerator for the maze routing problem is developed. This accelerator consists of three 3 stage pipelines. Banked memory is used to avoid memory read/write conflicts and obtain maximum efficiency.

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一种用于迷宫路由的硬件加速器

开发了一种用于迷宫路径问题的硬件加速器。该加速器由三个三级管道组成。存储内存是为了避免内存读/写冲突，获得最大的效率。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

24th ACM/IEEE Design Automation Conference

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