A Fast Signature Simulation Tool for Built-In Self-Testing Circuits

S. Tan, K. Totton, K. Baker, P. Varma, R. Porter
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引用次数: 8

Abstract

This paper describes a Fast Signature Simulator (FSS) tool for Built-In Self-Testing (BIST) circuits. The FSS consists of a simulator generator and a compiled code simulator. The simulator generator comprises a controlling program called the EXECUTIVE and translation software called SIM-GEN. SIM-GEN accepts a Hardware Description Language (HDL) representation of the circuit-under-test as its input and produces C code simulation modules comprising Boolean relations that represent the structure of the circuit. These C code modules are then compiled and linked together to form the basis of the compiled code simulator. Simulation is invoked by executing the compiled C code description of the circuit. The simulation time is minimised by the use of parallel simulation techniques in conjunction with efficient functional models and novel mapping techniques for the LFSRs. Performances approaching 5 Million Gate Evaluations Per Second (GEPS) have been achieved using the FSS.
用于内置自检电路的快速签名仿真工具
本文介绍了一种用于内置自检电路的快速签名模拟器(FSS)工具。FSS由模拟器生成器和编译代码模拟器组成。模拟器生成器由一个控制程序EXECUTIVE和翻译软件SIM-GEN组成。SIM-GEN接受被测电路的硬件描述语言(HDL)表示作为其输入,并生成包含表示电路结构的布尔关系的C代码仿真模块。然后将这些C代码模块编译并链接在一起,形成编译代码模拟器的基础。仿真是通过执行电路的编译C代码描述来调用的。通过使用并行仿真技术,结合高效的功能模型和新颖的lfsr映射技术,可以最大限度地减少仿真时间。使用FSS可以实现接近每秒500万次门评估(GEPS)的性能。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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