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Array Optimization for VLSI Synthesis VLSI合成中的阵列优化
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37968
D. F. Wong, C. Liu
{"title":"Array Optimization for VLSI Synthesis","authors":"D. F. Wong, C. Liu","doi":"10.1145/37888.37968","DOIUrl":"https://doi.org/10.1145/37888.37968","url":null,"abstract":"We present in this paper an algorithm that solves a general array optimization problem. The algorithm can be used for compacting Gate Matrix layouts, SLA's, Weinberger Arrays, and for multiple folding of PLA's. Our approach is based on the technique of simulated annealing. A major contribution of this paper is the formulation of the solution space which facilitates an effective search for an optimal solution. Experimental results are very encouraging.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"45 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134128042","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Accelerated Transition Fault Simulation 加速过渡故障模拟
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37923
Michael H. Schultz, F. Brglez
{"title":"Accelerated Transition Fault Simulation","authors":"Michael H. Schultz, F. Brglez","doi":"10.1145/37888.37923","DOIUrl":"https://doi.org/10.1145/37888.37923","url":null,"abstract":"This paper presents a new and an effective approach to fault simulation of transition faults in combinational or scan - based logic. An experiment with a set of benchmark circuits demonstrates the efficiency of the approach, achieved by combining a very fast single stuck - at fault simulation algorithm with a quasi - static definition of a transition fault. Tests that cover transition faults are becoming increasingly important as they also provide a cover for most typical transistor stuck - open faults in CMOS.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"41 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132182482","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 84
HPEX: A Hierarchical Parasitic Circuit Extractor HPEX:一种分层寄生电路提取器
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37975
S. Su, V. Rao, T. Trick
{"title":"HPEX: A Hierarchical Parasitic Circuit Extractor","authors":"S. Su, V. Rao, T. Trick","doi":"10.1145/37888.37975","DOIUrl":"https://doi.org/10.1145/37888.37975","url":null,"abstract":"A hierarchical parasitic circuit extractor HPEX for Manhattan layouts is described. HPEX can model interconnection lines as distributed lumped circuits directly from a circuit layout by using analytical formulas instead of numerical methods. The difference in feature sizes between mask layouts and actual fabricated conductors is also taken into account by a geometrical preprocessing algorithm based on a novel Y-X scanline method and a simple rectangle data structure. In addition, a simple and accurate node reduction technique based on the concept of Elmore's delay is employed in HPEX to make layout verification simpler. All features mentioned above clearly indicate that HPEX will be a promising tool in verifying VLSI system performance especially when interconnect parasitics associated with VLSI circuits are taken into consideration.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"1468 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133817927","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 20
Abstract Routing of Logic Networks for Custom Module Generation 自定义模块生成逻辑网络的抽象路由
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37922
S. Healey, W. Kubitz
{"title":"Abstract Routing of Logic Networks for Custom Module Generation","authors":"S. Healey, W. Kubitz","doi":"10.1145/37888.37922","DOIUrl":"https://doi.org/10.1145/37888.37922","url":null,"abstract":"This paper describes a switchbox-type router for custom VLSI module generation as performed by a module planner. A module is decomposed into abstract cells consisting of global routes and boolean functional specifications. Each abstract cell is given to a cell synthesizer which generates the circuit layout and through-the-cell routing. Abstract routing for a module planner is in some sense similar to switchbox routing to the degree that all of the routes are generated internally within a rectangular boundary (routes are coming from four sides). The principle difference with respect to standard switchbox routing is at the geometric level, where a cell synthesizer generates the routing conduction layers along with circuit devices for each abstract cell within this rectangular region. The aspects of this paper which are thought to be novel contributions are 1) a relative pin assignment algorithm for the abstract cells; 2) a global routing penalty function which not only considers previous routes, but also considers gate complexity within the cells; 3) an efficient optimization algorithm for minimizing the number of tracks running through the module.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114143084","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Tutorial: Reading and Reviewing the Common Schema for Electrical Design and Analysis 教程:阅读和复习电气设计和分析的通用方案
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37959
C. Parks
{"title":"Tutorial: Reading and Reviewing the Common Schema for Electrical Design and Analysis","authors":"C. Parks","doi":"10.1145/37888.37959","DOIUrl":"https://doi.org/10.1145/37888.37959","url":null,"abstract":"This tutorial introduces the language, tools, and methods used to develop an information model by an IEEE Task Team. The model identifies the data and data relationships necessary to define electrical products. Reviews are now required for consensus by technical experts who are also familiar with this subject matter. The model will be used to evaluate data transfer formats and establish their mappings without compromising proprietary data structures.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"220 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114155754","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Function Search from Behavioral Description of a Digital System 数字系统行为描述中的功能搜索
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37977
Jung-Gen Wu, W. Ho, Y. Hu, D. Yun, H. Yu
{"title":"Function Search from Behavioral Description of a Digital System","authors":"Jung-Gen Wu, W. Ho, Y. Hu, D. Yun, H. Yu","doi":"10.1145/37888.37977","DOIUrl":"https://doi.org/10.1145/37888.37977","url":null,"abstract":"We present a novel approach for automating the functional design of digital systems. Given a set of behavioral specifications, the objective is to produce an optimal functional design which minimizes certain design criteria. One distinct feature of this approach is adding the step of function minimization. That is, the abstraction of the primitive operations into a set of functions that generates the desired behavior attempts to minimize the cost of that set according to the design criteria. For this purpose, it is important to have a powerful search strategy which will lead to a near-optimal solution in a reasonable time. We have adopted best-first search (A (*) algorithm) as the general framework, and developed several domain-specific heuristic functions (h') which control the search process. Preliminary experimental results are reported.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"22 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125372141","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits 带观测路径合并的下标d算法在Brglez-Fujiwara电路上的基准运行
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37964
M. Ladjadj, J. McDonald
{"title":"Benchmark Runs of the Subscripted D-Algorithm with Observation Path Mergers on the Brglez-Fujiwara Circuits","authors":"M. Ladjadj, J. McDonald","doi":"10.1145/37888.37964","DOIUrl":"https://doi.org/10.1145/37888.37964","url":null,"abstract":"To speed up the test generation process, the Subscripted D-Algorithm (AALG) uses \"gang\" testing in its attempts to construct a single test pattern designed to test simultaneously as many faults as possible. Other techniques such as merger of the observation paths and multiple backtrace are also introduced. However, the main purpose of this paper is to report results of the runs of AALG on various benchmark circuits specifically the Brglez-Fujiwara Circuits.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"82 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122472316","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
PAMS: An Expert System for Parameterized Module Synthesis 参数化模块综合专家系统
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37995
T.M. Cesear, E. Iodice, C. Tsareff
{"title":"PAMS: An Expert System for Parameterized Module Synthesis","authors":"T.M. Cesear, E. Iodice, C. Tsareff","doi":"10.1145/37888.37995","DOIUrl":"https://doi.org/10.1145/37888.37995","url":null,"abstract":"An expert system has been developed which converts a description of transistor connectivity into a parameterized CMOS module. PAMS was designed to augment a standard cell environment by automatically generating special purpose modules parameterized in terms of area, speed, and power dissipation. Allowing parameterization differentiates PAMS from previous expert systems work in this field.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"279 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122166825","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
VLSI Circuit Testing Using an Adaptive Optimization Model 基于自适应优化模型的VLSI电路测试
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37948
Philip S. Yu, C. M. Krishna, Yann-Hang Lee
{"title":"VLSI Circuit Testing Using an Adaptive Optimization Model","authors":"Philip S. Yu, C. M. Krishna, Yann-Hang Lee","doi":"10.1145/37888.37948","DOIUrl":"https://doi.org/10.1145/37888.37948","url":null,"abstract":"The purpose of testing is to determine the correctness of the unit under test in come optimal way. One difficulty in meeting the optimality requirement is that the stochastic properties of the unit are usually unknown a priori. For instance, one might not know exactly the yield of a VLSI production line before one tests the chips made as a result. Given the probability of unit failure and the coverage of a test, the optimal test period is easy to obtain. However, the probability of failure is not usually known a priori. We therefore develop an optimal sequential testing strategy which estimates the production yield based on ongoing test results, and then use it to determine the optimal test period.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122201060","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories 随机存取和内容可寻址存储器并行测试的设计与算法
24th ACM/IEEE Design Automation Conference Pub Date : 1987-10-01 DOI: 10.1145/37888.37999
P. Mazumder, J. Patel, W. Fuchs
{"title":"Design and Algorithms for Parallel Testing of Random Access and Content Addressable Memories","authors":"P. Mazumder, J. Patel, W. Fuchs","doi":"10.1145/37888.37999","DOIUrl":"https://doi.org/10.1145/37888.37999","url":null,"abstract":"This paper presents a design strategy for efficient and comprehensive parallel testing of both Random Access Memory (RAM) and Content Addressable Memory (CAM). Based on this design for testability approach, parallel testing algorithms for CAMs and RAMs are developed for a broad class of pattern sensitive faults. The resulting test procedures are significantly more efficient than previous approaches. For example, the design for testability strategy allows an entire w word CAM to be read in just one operation with a resulting speed up in testing as high as w. In the case of an n bit RAM, the improvement in test efficiency is by a factor of O(√n). overall reduction in testing time is considerable for large size memories.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131760055","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 25
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