{"title":"General Purpose Router","authors":"R. Enbody, H. Du","doi":"10.1145/37888.37989","DOIUrl":"https://doi.org/10.1145/37888.37989","url":null,"abstract":"Numerous solutions to the problem of detailed routing of wires on a chip have been proposed for two routing layers but few are general enough to also handle switchboxes, more than two layers, variable channel widths, or multiple-layer problems with stacked terminals (3-D routing) without extensive modifications. We propose a different routing approach that not only can solve the two layer problem but the other problems as well. The inherent parallelism of the approach lead to a coarse-grained parallel algorithm.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"116 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114969864","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Transistor Sizing in CMOS Circuits","authors":"Mehmet A. Cirit","doi":"10.1145/37888.37906","DOIUrl":"https://doi.org/10.1145/37888.37906","url":null,"abstract":"The problem of optimally sizing transistors in a VLSI CMOS circuit is considered. Models and algorithms for performing optimization on a single path using RC-tree approximation are presented. The results of an automatic optimization procedure are discussed.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"15 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129918901","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Overview of the Penn State Design System","authors":"R. Owens, M. J. Irwin","doi":"10.1145/37888.37965","DOIUrl":"https://doi.org/10.1145/37888.37965","url":null,"abstract":"This paper overviews a CAD system under development at Penn State which will allow fast and near optimal implementation of a restricted class of VLSI architectures. Our target architectures are hierarchical mesh extensions of systolic meshes. Our target applications are primarily in the signal processing domain. The primitive components, at the lowest level in the mesh hierarchy, are one of the unique features of our target architectures. The CAD system under development includes: a tool for target architecture decomposition into primitive components, a tool for multi-level logic reduction for the primitive components; a tool for automatic gate placement within a primitive component; a tool for component placement within the target architecture; a high-level simulation tool; and a layout verification tool.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"153 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133983563","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Querying Part Hierarchies: A Knowledge-Based Approach","authors":"A. Rosenthal, S. Heiler","doi":"10.1145/37888.37938","DOIUrl":"https://doi.org/10.1145/37888.37938","url":null,"abstract":"Part Hierarchies are a fundamental datatype in CAD applications. But intelligent and efficient processing requires major extensions to DBMS data models, query languages, and processing algorithms. We explore formulations and execution algorithms for path-traversal queries. Hierarchy semantics are then exploited for spatial data and to intelligently choose an appropriate detail level for query output.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"124 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132969516","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Conceptual Framework for Designing ASIC Hardware","authors":"S. S. Leung, M. Shanblatt","doi":"10.1145/37888.37981","DOIUrl":"https://doi.org/10.1145/37888.37981","url":null,"abstract":"A conceptual framework consisting of the design process, the design space, and the design repertoire for ASIC hardware is presented. An Inter-Level Design Process Model (ILDP) is proposed as a general model for expressing and implementing hierarchical design methodologies. The proposed conceptual framework is an effective instrument for bridging the increasingly wider gap between application engineers and VLSI designers.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"31 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134540320","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Preliminary Investigation into Parallel Routing on a Hypercube Computer","authors":"K. Olukotun, T. Mudge","doi":"10.1145/37888.38016","DOIUrl":"https://doi.org/10.1145/37888.38016","url":null,"abstract":"This paper describes an experiment in which parallel routing is performed on a medium grained hypercube parallel processor having 64 processing elements. Each node is a complete 32-bit computer with 128 K-bytes of memory and is connected to the other nodes via a direct hypercube interconnection network. A new parallel routing algorithm was developed to exploit this parallel structure. It is a three step algorithm consisting of a global routing step, a boundary crossing placement step, and a detailed routing step. All steps can be performed in parallel. When applied to a standard benchmark it was able to route 95 % of the wires. The algorithm was also executed on a large mainframe computer using the same benchmark. The execution time was compared to that for the hypercube. The hypercube was about three times as fast.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133407506","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"A Parallel PLA Minimization Program","authors":"R. Galivanche, S. Reddy","doi":"10.1145/37888.37983","DOIUrl":"https://doi.org/10.1145/37888.37983","url":null,"abstract":"In this paper we report on an implementation of a parallel algorithm to minimize PLA realizations of logic functions. The algorithm is derived from a widely available PLA minimization program called ESPRESSO-MV. The parallel algorithm was implemented on a shared memory multicomputer system. In the course of development of the parallel algorithm, some changes were made to ESPRESSO-MV which resulted in lower computing time. Experimental results using 105 PLAs are included.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115131498","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"Finding the Optimal Variable Ordering for Binary Decision Diagrams","authors":"Steven J. Friedman, K. Supowit","doi":"10.1145/37888.37941","DOIUrl":"https://doi.org/10.1145/37888.37941","url":null,"abstract":"The ordered binary decision diagram is a canonical representation for Boolean functions, presented by Bryant as a compact representation for a broad class of interesting functions derived from circuits. However, the size of the diagram is very sensitive to the choice of ordering on the variables; hence for some applications, such as Differential Cascode Voltage Switch (DCVS) trees, it becomes extremely important to find the ordering leading to the most compact representation. We present an algorithm for this problem with time complexity O(n/sup 2/3/sup n/), an improvement over the previous best, which required O(n!2/sup n/).","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"20 8","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131849892","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A. Vladimirescu, David Weiss, M. Katevenis, Z. Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, N. Jain, S. Lass
{"title":"A Vector Hardware Accelerator with Circuit Simulation Emphasis","authors":"A. Vladimirescu, David Weiss, M. Katevenis, Z. Bronstein, Alon Kifir, Karja Danuwidjaja, K. C. Ng, N. Jain, S. Lass","doi":"10.1145/37888.37901","DOIUrl":"https://doi.org/10.1145/37888.37901","url":null,"abstract":"A floating-point vector accelerator has been built which runs circuit simulation efficiently. The design considerations of the accelerator are based on the time-consuming parts of SPICE2, available off-the-shelf parts, advanced software tools experience and cost/performance. The three board accelerator can run the entire application program complied from a high-level language. A personal workstation, such as the PC-AT, is used for the general I/O tasks such as file handling and network support. The processor has a Single-Instruction Multiple-Data 64-bit floating-point pipelined architecture. It can achieve a maximum speed of 8 Mips and 8 MFlops. A floating-point processor based on two functional units, a multiplier and an ALU, and an integer processor work in parallel to achieve the high performance. The accelerator attached to a PC-AT runs SPICE2 60 times faster than the personal workstation alone and achieves double the performance of a VAX 8650.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125091967","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
{"title":"An Automatic Rectilinear Partitioning Procedure for Standard Cells","authors":"Mely Chen Chi","doi":"10.1145/37888.37895","DOIUrl":"https://doi.org/10.1145/37888.37895","url":null,"abstract":"This paper describes a new approach to automatically partition and place the standard cells in a rectilinear area on a chip among the pre-placed macro cells (RAM, ROM, PLA etc.) and I/O pads. The macro cells may be placed anywhere on the chip. The topological and physical constraints, and the net list connectivity are accounted for simultaneously. This procedure has been implemented in the AT&T Bell Laboratories LTX2 chip layout system.","PeriodicalId":301552,"journal":{"name":"24th ACM/IEEE Design Automation Conference","volume":"48 10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1987-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130417126","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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