PLAY: Pattern-Based Symbolic Cell Layout Part I: Transistor Placement

Abstract

This paper describes an approach to symbolic transistor placement from a CMOS circuit net-list as part of an automatic custom cell layout system, PLAY. It consists of two parts, extraction and refinement. The extraction process defines a set of patterns using local connection relationships. Refinement procedures assign topological attributes to each transistor through these patterns and relationships along with other heuristic knowledge. This paradigm provides a new way to embed designers' knowledge for circuit layout. Although only CMOS circuit layout placements are demonstrated, this approach can readily be extended to other technologies. Comparison between PLAY and manual design results is also reported.