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Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)最新文献

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A new digital to analog converter resistor string architecture 一种新的数模转换电阻串结构
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617026
P.K. Oborn, D. Comer
{"title":"A new digital to analog converter resistor string architecture","authors":"P.K. Oborn, D. Comer","doi":"10.1109/ASIC.1997.617026","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617026","url":null,"abstract":"This paper introduces a resistor string architecture for implementing a digital to analog converter on a CMOS circuit process. The proposed circuit maintains the advantages of guaranteed monotonicity inherent in previous resistor string architectures but provides a higher efficiency of resistor usage. Using \"virtual resistance coding\" it is possible to obtain a very high integral and differential linearities (/spl sim/0% LSB). Likewise, this DAC architecture requires only one buffer amplifier, offering potential high-speed operation.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"33 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"128530422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010 预测高性能，最低功耗CMOS ASIC技术:1998-2010
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617002
A. Bhavnagarwala, B. Austin, J. Meindl
{"title":"Projections for high performance, minimum power CMOS ASIC technologies: 1998-2010","authors":"A. Bhavnagarwala, B. Austin, J. Meindl","doi":"10.1109/ASIC.1997.617002","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617002","url":null,"abstract":"Circuit design techniques minimizing total power drain of a static CMOS gate for a prescribed performance and an operating range of temperatures are employed to project supply voltages, power densities, device threshold voltages and critical path device channel widths for CMOS ASIC technology generations listed in the 1994 NTRS (National Technology Roadmap for Semiconductors) up to the year 2010. These projections are consistent with 1994 NTRS technology and cycle time forecasts and use physical and stochastic models that tightly couple together the device, circuit and system levels of the CMOS ASIC design hierarchy. Verified by HSPICE and actual microprocessor implementations, these models project optimal supply voltages for 0.25-0.07 /spl mu/m generations to scale from 900 mV to 500 mV and power densities to increase from 3 W/cm/sup 2/ to 10 W/cm/sup 2/ in wire limited high performance CMOS ASIC systems.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"77 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131074547","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach 使用MOS PTAT的低功耗CMOS片上电压基准:一种EP方法
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617029
Yoon-Deuk Seo, D. Nam, Byoung-Jin Yoon, I. Choi, Beomsup Kim
{"title":"Low-power CMOS on-chip voltage reference using MOS PTAT: an EP approach","authors":"Yoon-Deuk Seo, D. Nam, Byoung-Jin Yoon, I. Choi, Beomsup Kim","doi":"10.1109/ASIC.1997.617029","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617029","url":null,"abstract":"This paper presents a new low-power on-chip voltage reference less sensitive to the process variation in an 0.5 /spl mu/m DRAM process where neither reliable BJT nor depletion MOS are available. The proposed voltage reference uses the MOS threshold voltage and a PTAT (proportional to the absolute temperature) voltage generated only from MOS transistors, and achieves considerably good performance at the total current of less than 8 /spl mu/A with an external power supply voltage ranging from 2.8 to 4 V. The measured temperature coefficient is about 360 ppm//spl deg/C at temperatures ranging from 0/spl deg/C to 100/spl deg/C. In addition, an optimization technique is proposed to find a set of optimal parameters in designing circuits.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"120 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"122474528","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
Testable VLSI circuit design of SIMD graphics engine 可测试的SIMD图形引擎VLSI电路设计
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616981
D. Pok, C.-i.H. Chen
{"title":"Testable VLSI circuit design of SIMD graphics engine","authors":"D. Pok, C.-i.H. Chen","doi":"10.1109/ASIC.1997.616981","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616981","url":null,"abstract":"In every computer graphics system, there is some interaction between a special memory called a frame buffer and a computation engine. It is the architecture between these two that determines how fast, flexible, and expensive the graphics subsystem is. In this paper, we present the testability analysis and chip testing of Enhanced Memory Chip (EMC) using the scan-BIST (built-in self-test) partial scan scenario. EMC is a multi-million transistors graphics computation engine produced by WL/AASE, WPAFB in VHDL formats and is fabricated using 0.5 /spl mu/m CMOS technology. Fundamentally, it is memory that is enhanced with tightly-coupled computational logic on the same chip. The logic is arranged in a single instruction, multiple data architecture that can efficiently perform the linear expression evaluation that is common in the lowest level graphic rasterization. The fault simulation shows that partial scan scenario is feasible for EMC and generates scan-BIST high fault coverage and low overhead.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"62 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133117702","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Applying functional decomposition for depth minimal technology mapping of multiplexer based FPGAs 应用函数分解实现基于多路复用器的fpga深度最小技术映射
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616987
C. Yeh
{"title":"Applying functional decomposition for depth minimal technology mapping of multiplexer based FPGAs","authors":"C. Yeh","doi":"10.1109/ASIC.1997.616987","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616987","url":null,"abstract":"Functional decomposition has undergone intensive study in recent literature and gained great success in technology mapping for lookup-table based FPGAs. Yet none has ever attempted at extending such success to other applications. In this work, we move one step further by choosing the multiplexer based FPGAs as the new test bed. Using a typical algorithmic framework and the benchmark test set, we show that functional decomposition can be easily adapted to reduce the logic depth of the mapped network without incurring massive area penalty.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114294274","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Boundary scan adaption for active substrate MCM-test 有源衬底mcm测试的边界扫描自适应
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616979
H. Werkmann, B. Hofflinger, B. Laquai
{"title":"Boundary scan adaption for active substrate MCM-test","authors":"H. Werkmann, B. Hofflinger, B. Laquai","doi":"10.1109/ASIC.1997.616979","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616979","url":null,"abstract":"A MCM test strategy using boundary scan-cells integrated into silicon substrates is presented. The differences between IC-based boundary scan and active substrate boundary scan and their effects on scan-cell placement and design are highlighted. A yield optimized partition of the test circuitry and an adaption to commercially available boundary scan test systems is proposed. Active substrates with boundary scan test capabilities are fabricated based on the identified requirements. The adaption to the test system is evaluated.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"7 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129730419","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Lorentz force MOS transistor 洛伦兹力MOS晶体管
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617024
T. Gabara
{"title":"Lorentz force MOS transistor","authors":"T. Gabara","doi":"10.1109/ASIC.1997.617024","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617024","url":null,"abstract":"A new set of terminals has been introduced to control the behavior of an MOS device. A magnetic field, formed when current flows through an on-chip coil, is applied to the inversion layer of an MOS device. The generated Lorentz force is applied to the carriers in the inversion layer to alter the characteristics of the MOS device. The magnetic field is applied parallel to the inversion layer and perpendicular to the carrier flow. Measurement results using this structure as a 1.8 GHz mixer are given. Measurements demonstrate that the interaction between the coil and the MOS device is primarily due to the Lorentz force. The capacitive coupling effect between the coil and the device plays a minor role.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130199772","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Efficient redundancy identification for test pattern generation 测试模式生成的高效冗余识别
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616977
Sangyun Han, Sungho Kang
{"title":"Efficient redundancy identification for test pattern generation","authors":"Sangyun Han, Sungho Kang","doi":"10.1109/ASIC.1997.616977","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616977","url":null,"abstract":"Due to the reconvergent fanouts which make the dependency among objectives and block the fault propagation, there may exist redundant faults in the circuits. This paper presents the isomorphism identification algorithm and the pseudo dominator algorithm which are used to identify redundant faults. Experimental results on ISCAS 85 benchmark circuits show that these algorithms are efficient in identifying redundant faults.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"129210360","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low power optimization of bit-serial digital filters 位串行数字滤波器的低功耗优化
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617011
P. Astrom, P. Nilsson, M. Torkelsson
{"title":"Low power optimization of bit-serial digital filters","authors":"P. Astrom, P. Nilsson, M. Torkelsson","doi":"10.1109/ASIC.1997.617011","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617011","url":null,"abstract":"A new approach to optimize full custom, fixed coefficient bit-serial filters aimed at high sample rate and low power consumption is presented. The idea is to trade the filter order with the coefficient length. To show the results two filters were designed and implemented, one as a minimum order filter and the other as a minimum coefficient filter. Measurements shows that a ten fold increase in sample rate can be obtained at half the power consumption.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"48 2","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114023403","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
On the relationship among accuracy, tolerance and compensation in the deep sub-micron era 深亚微米时代精度、公差与补偿的关系
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616986
D. Hill, A. Domic
{"title":"On the relationship among accuracy, tolerance and compensation in the deep sub-micron era","authors":"D. Hill, A. Domic","doi":"10.1109/ASIC.1997.616986","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616986","url":null,"abstract":"Historically, ASIC solutions tended to be effective because the physics and scale of most production technologies allowed circuit designers (and circuit design tools) to safely abstract physical properties: the size and performance of chips could largely be predicted based on logical structure alone. But those days are going fast, and with the advent of 500 K+ gate chips in deep sub-micron (DSM) technologies, new approaches must be found, This paper starts with some background in technology trends, and then reviews the traditional \"over the wall\" methodology. Section 3 then proposes a \"limited loops\" design flow based on estimation, floorplanning, and the effective cooperation of synthesis and gate-level placement technologies. This flow is discussed from the perspective of error in the estimation processes and the ability of subsequent steps to tolerate and compensate for the error.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"352 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115976460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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