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Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)最新文献

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Process, voltage and temperature compensation of off-chip-driver circuits for sub-0.25-/spl mu/m CMOS technology 低于0.25-/spl μ m CMOS技术的片外驱动电路的工艺、电压和温度补偿
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617021
H. Chi, D. Stout, J. Chickanosky
{"title":"Process, voltage and temperature compensation of off-chip-driver circuits for sub-0.25-/spl mu/m CMOS technology","authors":"H. Chi, D. Stout, J. Chickanosky","doi":"10.1109/ASIC.1997.617021","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617021","url":null,"abstract":"A control circuit that compensates for variations in process, voltage and temperature (PVT) has been developed to control off-chip-driver circuits used for sub-0.25-/spl mu/m technology. The off-chip-driver (OCD), alone with a simple control scheme, delivers a tight impedance tolerance at the output, improving the output signal waveforms. Across-chip length variation (ACLV), the controlled-circuit design and off-chip-driver performance are also discussed.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"19 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133618033","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Low-voltage floating-gate current mirrors 低压浮栅电流反射镜
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616971
Y. Berg, T. Lande, S. Naess
{"title":"Low-voltage floating-gate current mirrors","authors":"Y. Berg, T. Lande, S. Naess","doi":"10.1109/ASIC.1997.616971","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616971","url":null,"abstract":"In this paper we propose a novel design of low-voltage current mirrors using floating gates. Floating gate UV-light programmable MOS transistors (FGUVMOS) are used to design current mirrors in low-voltage/low-power analog applications. The capacitive divider inputs to the floating gates can he utilized to reduce current mismatch due to Early effect.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"18 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116655187","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 24
A low power high speed error correction code macro using complementary pass transistor logic circuit 一种采用互补通型晶体管逻辑电路的低功耗高速纠错码宏
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616970
L.K. Wang, H.H. Chen
{"title":"A low power high speed error correction code macro using complementary pass transistor logic circuit","authors":"L.K. Wang, H.H. Chen","doi":"10.1109/ASIC.1997.616970","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616970","url":null,"abstract":"This paper describes the design and implementation of the complementary pass transistor logic (CPL) circuit in a CMOS macro design. The power, speed and noise margin of pass-transistor logic circuits are evaluated and the transistor sizes are optimized for noise margin and circuit performance. This circuit has been successfully implemented in a 64-bit Error Correction Code (ECC) and parity checking macro in the IBM S/390 CMOS processor and significantly improves the power and speed of the ECC macro performance.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"325 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115870659","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
Substrate coupling in mixed-mode and RF integrated circuits 混合模式和射频集成电路中的衬底耦合
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617025
N. Verghese, D. Allstot
{"title":"Substrate coupling in mixed-mode and RF integrated circuits","authors":"N. Verghese, D. Allstot","doi":"10.1109/ASIC.1997.617025","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617025","url":null,"abstract":"This paper overviews substrate coupling in mixed mode and RF integrated circuits. Verification methods are reviewed with emphasis on modeling techniques for the substrate. An efficient substrate coupling simulation methodology is presented that utilizes macromodels of the circuit, substrate and package, and a design example is illustrated.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114924742","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
An improved silicon retina chip with optical input and optical output 一种改进的带有光输入和光输出的硅视网膜芯片
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616984
A. Titus, T. Drabik
{"title":"An improved silicon retina chip with optical input and optical output","authors":"A. Titus, T. Drabik","doi":"10.1109/ASIC.1997.616984","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616984","url":null,"abstract":"This paper describes a unique implementation of an optical-in/optical-out focal-plane processor with improved performance and increased control over the output that uses differential difference amplifiers and a clocked-analog scheme. This is accomplished on a single chip and represents a step toward creating a low-power, compact, visual processing system.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"87 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"126069600","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 5
Automatic feasibility/performance estimation of mixed-signal circuits based on design specifications 基于设计规范的混合信号电路可行性/性能自动估计
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616989
Kyung-Im Son, Heung-Joon Park, M. Soma
{"title":"Automatic feasibility/performance estimation of mixed-signal circuits based on design specifications","authors":"Kyung-Im Son, Heung-Joon Park, M. Soma","doi":"10.1109/ASIC.1997.616989","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616989","url":null,"abstract":"This paper proposes a new technique to estimate the feasibility/performance surfaces of mixed-signal circuits. The estimates will be used to construct a multi-class classifier which can be used as an automatic topology selector for the top-down design of analog circuits. The technique employs an ANN classification algorithm that requires no a priori knowledge of the complexity or shape of estimated surfaces. The estimation is optimized with respect to the training data size using a query-based data growing technique. As a case study, the feasibility/performance surfaces of sub-circuits in a 2nd order /spl Sigma/-/spl Delta/ ADC are estimated. The estimation results confirm the generality of the proposed method. Estimated surfaces can be updated swiftly as the process technology evolves, which makes our technique nearly process technology independent.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127676073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A modern ASIC controller for a 6-pulse rectifier 用于6脉冲整流器的现代ASIC控制器
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617032
M. Cirstea, M. G. Giamusi, M. McCormick
{"title":"A modern ASIC controller for a 6-pulse rectifier","authors":"M. Cirstea, M. G. Giamusi, M. McCormick","doi":"10.1109/ASIC.1997.617032","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617032","url":null,"abstract":"This paper illustrates the advantages of silicon implementation of a digital controller for 3-phase 6-pulse power rectifiers, using Electronic Design Automation (EDA) techniques. The control Application Specific Integrated Circuit (ASIC) was simulated and then implemented into a XILINX Field Programmable Gate Array (FPGA). The paper describes the practical achievement of a new zero crossing detection circuit for the six line-to-line power voltages, which eliminates the use of transformers and performs a good galvanic isolation in conjunction with a high noise immunity. The complete 6-pulse controller including the ASIC, the zero-crossing detector and an interface circuit was commissioned and is currently being comprehensively tested.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"3 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117314950","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Mixed-signal considerations when integrating systems 集成系统时的混合信号考虑
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617009
R. Franzo, M. Diamondstein, L. Rigge, Steve Vandris
{"title":"Mixed-signal considerations when integrating systems","authors":"R. Franzo, M. Diamondstein, L. Rigge, Steve Vandris","doi":"10.1109/ASIC.1997.617009","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617009","url":null,"abstract":"Companies such as Lucent Technologies, which was involved in pioneering efforts such as the AT&T DSP16C in 1989, have been integrating mixed-signal and DSP for close to ten years. New techniques and expertise support integration earlier in the product life-cycle with minimal risk. In fact, many mixed-signal integrated solutions implemented by Lucent's technical staff achieved fully functional first silicon. Techniques such as those described in this paper are necessary steps along the way to achieving fully integrated digital communication ultrachips.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"10 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123740036","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An easy approach to formal verification 一种简单的形式验证方法
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616990
T. Schlipf, T. Buchner, R. Fritz, M. Helms
{"title":"An easy approach to formal verification","authors":"T. Schlipf, T. Buchner, R. Fritz, M. Helms","doi":"10.1109/ASIC.1997.616990","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616990","url":null,"abstract":"Formal verification suffers from the image that it is complicated and requires a lot of mathematical background to be applied successfully. In this paper a methodology is described that adds formal verification (FV) to the verification process without requiring any knowledge of FV languages. It solely uses the finite state machine notation, which is familiar and intuitive to designers. Another problem of FV is state space explosion. If this occurs we can switch to random simulation within an hour without losing any effort. The results show that FV is at least as fast as random simulation and it is superior in terms of verification quality because it is exhaustive.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121203054","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Design issues for flip-chip ICs in multilayer packages 多层封装倒装ic的设计问题
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617017
R. Frye
{"title":"Design issues for flip-chip ICs in multilayer packages","authors":"R. Frye","doi":"10.1109/ASIC.1997.617017","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617017","url":null,"abstract":"Flip-chip area array attachment, originally developed for MCM offers IC size reduction and improved operating speed, especially for high-end ASICs with large numbers of I/O. It is also proving to be well-suited for use in single-chip BGA packages. A key problem for most designers having limited experience with the technology, however, is the lack of a widely accepted design methodology. This paper examines the advantages of the flip-chip structure discusses emerging physical design methodologies and points out some of the remaining challenges in flip-chip ASIC design.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"1 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"130961996","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
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