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Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)最新文献

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A general method to double the cycle simulation speed 一种将周期仿真速度提高一倍的通用方法
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617037
H. Gerst
{"title":"A general method to double the cycle simulation speed","authors":"H. Gerst","doi":"10.1109/ASIC.1997.617037","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617037","url":null,"abstract":"Cycle simulation is a well known method for high speed simulation. The technique of reducing master/slave latch pairs to single latches is also known, however, only if the master/slave latch pairs are used as defined. Today's highly optimized hardware designs use master/slave latches in such a general way, that a reduction to single latches has become a challenge. This paper shows a method to reach single latch models. General simulation problems of single latch models are also discussed.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115373073","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
A unique section overhead processor for STM-64 STM-64独有的分段开销处理器
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616997
T. Lee, J. Cho, Jeong-Hoon Ko
{"title":"A unique section overhead processor for STM-64","authors":"T. Lee, J. Cho, Jeong-Hoon Ko","doi":"10.1109/ASIC.1997.616997","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616997","url":null,"abstract":"A Unique CMOS Section Overhead (SOH) processor has been designed for use in 10 Gbit/s SDH-based optical transmission system. A uniquely structured chip makes it possible to use parallel processing of STM-64 SOH at low speed with four identical chips. The features supported by the chips include STM-64 SOH insertion and extraction including Regenerator Section Trace (RST), frame alignment word insertion, alarm detection and generation, and performance monitoring. This paper introduces a novel parallel circuit design methodology for processing STM-64 SOH and describes the unique architecture, implementation and experimental test results of the chip, SOH processor. This paper also presents the implementation methodology of RST using CRC-7 polynomial algorithm.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117276269","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
An accurate, computationally efficient crosstalk model for routing high-speed MCMs 一种精确、计算效率高的高速mcm串扰路由模型
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616988
K.J. McClellan, T.S. Wailes, P. Franzon
{"title":"An accurate, computationally efficient crosstalk model for routing high-speed MCMs","authors":"K.J. McClellan, T.S. Wailes, P. Franzon","doi":"10.1109/ASIC.1997.616988","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616988","url":null,"abstract":"A crosstalk model that is both accurate and easily incorporated into an MCM router has been developed. This model accounts for coupling from multiple layers out to three wires in either direction and accounts for the shielding involved with those wires. An algorithm that calculates the effect of reflections from terminals with mismatched impedances is also included as part of the model. Finally,it is shown to be impractical to use a more complex crosstalk model without including some sort of timing simulator.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115091588","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
A MAGFET sensor array for digital magnetic signal reading 用于数字磁信号读取的磁场效应晶体管传感器阵列
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617027
S. Rohrer, S. Hentschke, N. Reifschneider
{"title":"A MAGFET sensor array for digital magnetic signal reading","authors":"S. Rohrer, S. Hentschke, N. Reifschneider","doi":"10.1109/ASIC.1997.617027","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617027","url":null,"abstract":"A sensor array consisting of MAGFETs and stochastic flip flop cells is proposed for the direct reading of magnetically stored information. A following adaptive filter provides the autocalibration of the flip flop cells by means of a biasing charge-pump and ensures the detection of the digital magnetic data for low over-sampling rates.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114430348","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 6
Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries 布局验证，以提高缩小CMOS单元库的ESD/闭锁抗扰度
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616991
M. Ker, Sue-Mei Hsiao, Jiann-Horng Lin
{"title":"Layout verification to improve ESD/latchup immunity of scaled-down CMOS cell libraries","authors":"M. Ker, Sue-Mei Hsiao, Jiann-Horng Lin","doi":"10.1109/ASIC.1997.616991","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616991","url":null,"abstract":"Layout verification has been proposed to improve the ESD (Electrostatic Discharge) and latchup immunity of scaled-down CMOS cell libraries. By using the DRC (design rules check) and ERC (electrical rules check), the ESD/latchup sensitive layout can be found. By changing the layout in the suggested way of high immunity to ESD and latchup without increasing the layout area of the cells, the ESD and latchup reliability of CMOS IC's assembled by the layout-verified cell libraries can be significantly improved.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114334301","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Challenges and approaches in mixed signal RF testing 混合信号射频测试的挑战与方法
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616973
Mani Soma
{"title":"Challenges and approaches in mixed signal RF testing","authors":"Mani Soma","doi":"10.1109/ASIC.1997.616973","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616973","url":null,"abstract":"This paper describes the challenges and indicates possible approaches in RF testing, focusing on digital systems, analog subsystems, and integrated mixed-signal systems. The approaches to innovative test techniques to reduce dependence on external automatic test equipment and to mitigate the analog test issues lead to a proposed integrated framework to serve as basis for future test developments. The interdependence between simulation and test is identified to support the framework and eliminate unnecessary test.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125711436","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 21
A portable printer controller ASIC design using behavioral compiler 用行为编译器设计便携式打印机的ASIC控制器
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616983
T. Chan, B. Yeh
{"title":"A portable printer controller ASIC design using behavioral compiler","authors":"T. Chan, B. Yeh","doi":"10.1109/ASIC.1997.616983","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616983","url":null,"abstract":"This paper describes the implementation of a complex image processing algorithm for a portable printer controller ASIC. The ASIC design and development process employs Synopsys's Behavioral Compiler as a new design methodology. This paper discusses the error diffusion image processing algorithm as an illustrative algorithm so as to better share the benefits and the difficulties when implementing such an algorithm using Behavioral Compiler.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"134482532","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Low voltage and low power design of microwave mixer 微波混合器的低电压低功耗设计
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617036
E. Allamando L, P.E. Gosse
{"title":"Low voltage and low power design of microwave mixer","authors":"E. Allamando L, P.E. Gosse","doi":"10.1109/ASIC.1997.617036","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617036","url":null,"abstract":"K-band mixers are realised on GaAs MMIC technology by employing cold FET devices. With this submicrometer device, two configurations are studied and realized: the \"series\" and the \"shunt\". Experimental results are compared to theoretical predictions obtained on microwave nonlinear simulator by using an original modelling of the cold FET.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"114507596","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Boundary scan access of built-in self-test for field programmable gate arrays 现场可编程门阵列内置自检的边界扫描访问
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.616978
G. Gibson, L. Gray, C. Stroud
{"title":"Boundary scan access of built-in self-test for field programmable gate arrays","authors":"G. Gibson, L. Gray, C. Stroud","doi":"10.1109/ASIC.1997.616978","DOIUrl":"https://doi.org/10.1109/ASIC.1997.616978","url":null,"abstract":"We discuss issues associated with system level access of Built-In Self-Test (BIST) for Field Programmable Gate Arrays (FPGAs) via the Boundary Scan Interface. In addition, we describe the design of an Application Specific Integrated Circuit (ASIC) which serves as an interface between a PC parallel port and the Test Access Port (TAP) of one or more FPGAs to reprogram the FPGA(s) and administer BIST during off-line testing. We also include a brief description of the FPGA BIST architecture and operation.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"115034173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 9
A reconfigurable hardware accelerator for moment computation 用于力矩计算的可重构硬件加速器
Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI: 10.1109/ASIC.1997.617013
D. Hung, H. D. Cheng, S. Sengkhamyong
{"title":"A reconfigurable hardware accelerator for moment computation","authors":"D. Hung, H. D. Cheng, S. Sengkhamyong","doi":"10.1109/ASIC.1997.617013","DOIUrl":"https://doi.org/10.1109/ASIC.1997.617013","url":null,"abstract":"In image processing, moment-invariant is one of the most useful methods for feature extraction. However, real-time applications of this method have been prohibited due to the intensive computation required in calculating the moments of an image. This paper describes a hardware solution to this problem.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"132019076","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 2
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