{"title":"A unique section overhead processor for STM-64","authors":"T. Lee, J. Cho, Jeong-Hoon Ko","doi":"10.1109/ASIC.1997.616997","DOIUrl":null,"url":null,"abstract":"A Unique CMOS Section Overhead (SOH) processor has been designed for use in 10 Gbit/s SDH-based optical transmission system. A uniquely structured chip makes it possible to use parallel processing of STM-64 SOH at low speed with four identical chips. The features supported by the chips include STM-64 SOH insertion and extraction including Regenerator Section Trace (RST), frame alignment word insertion, alarm detection and generation, and performance monitoring. This paper introduces a novel parallel circuit design methodology for processing STM-64 SOH and describes the unique architecture, implementation and experimental test results of the chip, SOH processor. This paper also presents the implementation methodology of RST using CRC-7 polynomial algorithm.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.616997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
A Unique CMOS Section Overhead (SOH) processor has been designed for use in 10 Gbit/s SDH-based optical transmission system. A uniquely structured chip makes it possible to use parallel processing of STM-64 SOH at low speed with four identical chips. The features supported by the chips include STM-64 SOH insertion and extraction including Regenerator Section Trace (RST), frame alignment word insertion, alarm detection and generation, and performance monitoring. This paper introduces a novel parallel circuit design methodology for processing STM-64 SOH and describes the unique architecture, implementation and experimental test results of the chip, SOH processor. This paper also presents the implementation methodology of RST using CRC-7 polynomial algorithm.