{"title":"一种将周期仿真速度提高一倍的通用方法","authors":"H. Gerst","doi":"10.1109/ASIC.1997.617037","DOIUrl":null,"url":null,"abstract":"Cycle simulation is a well known method for high speed simulation. The technique of reducing master/slave latch pairs to single latches is also known, however, only if the master/slave latch pairs are used as defined. Today's highly optimized hardware designs use master/slave latches in such a general way, that a reduction to single latches has become a challenge. This paper shows a method to reach single latch models. General simulation problems of single latch models are also discussed.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"73 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A general method to double the cycle simulation speed\",\"authors\":\"H. Gerst\",\"doi\":\"10.1109/ASIC.1997.617037\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"Cycle simulation is a well known method for high speed simulation. The technique of reducing master/slave latch pairs to single latches is also known, however, only if the master/slave latch pairs are used as defined. Today's highly optimized hardware designs use master/slave latches in such a general way, that a reduction to single latches has become a challenge. This paper shows a method to reach single latch models. General simulation problems of single latch models are also discussed.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"73 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.617037\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.617037","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
A general method to double the cycle simulation speed
Cycle simulation is a well known method for high speed simulation. The technique of reducing master/slave latch pairs to single latches is also known, however, only if the master/slave latch pairs are used as defined. Today's highly optimized hardware designs use master/slave latches in such a general way, that a reduction to single latches has become a challenge. This paper shows a method to reach single latch models. General simulation problems of single latch models are also discussed.