STM-64独有的分段开销处理器

Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334) Pub Date : 1997-09-07 DOI:10.1109/ASIC.1997.616997

T. Lee, J. Cho, Jeong-Hoon Ko

{"title":"STM-64独有的分段开销处理器","authors":"T. Lee, J. Cho, Jeong-Hoon Ko","doi":"10.1109/ASIC.1997.616997","DOIUrl":null,"url":null,"abstract":"A Unique CMOS Section Overhead (SOH) processor has been designed for use in 10 Gbit/s SDH-based optical transmission system. A uniquely structured chip makes it possible to use parallel processing of STM-64 SOH at low speed with four identical chips. The features supported by the chips include STM-64 SOH insertion and extraction including Regenerator Section Trace (RST), frame alignment word insertion, alarm detection and generation, and performance monitoring. This paper introduces a novel parallel circuit design methodology for processing STM-64 SOH and describes the unique architecture, implementation and experimental test results of the chip, SOH processor. This paper also presents the implementation methodology of RST using CRC-7 polynomial algorithm.","PeriodicalId":300310,"journal":{"name":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","volume":"50 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1997-09-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":"{\"title\":\"A unique section overhead processor for STM-64\",\"authors\":\"T. Lee, J. Cho, Jeong-Hoon Ko\",\"doi\":\"10.1109/ASIC.1997.616997\",\"DOIUrl\":null,\"url\":null,\"abstract\":\"A Unique CMOS Section Overhead (SOH) processor has been designed for use in 10 Gbit/s SDH-based optical transmission system. A uniquely structured chip makes it possible to use parallel processing of STM-64 SOH at low speed with four identical chips. The features supported by the chips include STM-64 SOH insertion and extraction including Regenerator Section Trace (RST), frame alignment word insertion, alarm detection and generation, and performance monitoring. This paper introduces a novel parallel circuit design methodology for processing STM-64 SOH and describes the unique architecture, implementation and experimental test results of the chip, SOH processor. This paper also presents the implementation methodology of RST using CRC-7 polynomial algorithm.\",\"PeriodicalId\":300310,\"journal\":{\"name\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"volume\":\"50 1\",\"pages\":\"0\"},\"PeriodicalIF\":0.0000,\"publicationDate\":\"1997-09-07\",\"publicationTypes\":\"Journal Article\",\"fieldsOfStudy\":null,\"isOpenAccess\":false,\"openAccessPdf\":\"\",\"citationCount\":\"0\",\"resultStr\":null,\"platform\":\"Semanticscholar\",\"paperid\":null,\"PeriodicalName\":\"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)\",\"FirstCategoryId\":\"1085\",\"ListUrlMain\":\"https://doi.org/10.1109/ASIC.1997.616997\",\"RegionNum\":0,\"RegionCategory\":null,\"ArticlePicture\":[],\"TitleCN\":null,\"AbstractTextCN\":null,\"PMCID\":null,\"EPubDate\":\"\",\"PubModel\":\"\",\"JCR\":\"\",\"JCRName\":\"\",\"Score\":null,\"Total\":0}","platform":"Semanticscholar","paperid":null,"PeriodicalName":"Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ASIC.1997.616997","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}

引用次数: 0

摘要

设计了一种独特的CMOS分段开销(SOH)处理器，用于基于10gbit /s sdh的光传输系统。一个独特的结构芯片使得可以使用STM-64 SOH的并行处理在低速与四个相同的芯片。芯片支持的功能包括STM-64 SOH插入和提取，包括Regenerator Section Trace (RST)、帧对齐字插入、报警检测和生成以及性能监控。本文介绍了一种处理STM-64 SOH的新型并行电路设计方法，并介绍了该芯片SOH处理器的独特结构、实现和实验测试结果。本文还介绍了使用CRC-7多项式算法实现RST的方法。

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A unique section overhead processor for STM-64

A Unique CMOS Section Overhead (SOH) processor has been designed for use in 10 Gbit/s SDH-based optical transmission system. A uniquely structured chip makes it possible to use parallel processing of STM-64 SOH at low speed with four identical chips. The features supported by the chips include STM-64 SOH insertion and extraction including Regenerator Section Trace (RST), frame alignment word insertion, alarm detection and generation, and performance monitoring. This paper introduces a novel parallel circuit design methodology for processing STM-64 SOH and describes the unique architecture, implementation and experimental test results of the chip, SOH processor. This paper also presents the implementation methodology of RST using CRC-7 polynomial algorithm.

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Proceedings. Tenth Annual IEEE International ASIC Conference and Exhibit (Cat. No.97TH8334)

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