Applying functional decomposition for depth minimal technology mapping of multiplexer based FPGAs

Functional decomposition has undergone intensive study in recent literature and gained great success in technology mapping for lookup-table based FPGAs. Yet none has ever attempted at extending such success to other applications. In this work, we move one step further by choosing the multiplexer based FPGAs as the new test bed. Using a typical algorithmic framework and the benchmark test set, we show that functional decomposition can be easily adapted to reduce the logic depth of the mapped network without incurring massive area penalty.