2019 Devices for Integrated Circuit (DevIC)最新文献_第8页

A Low Power Hardware Implementation of Lifting based Reversible Watermarking for Medical Image 基于提升的医学图像可逆水印的低功耗硬件实现

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783370

Poulami Jana, G. Maity, Himadri S. Mandal

引用次数: 1

SPICE Parameter Extraction of Tri-Gate FinFETs-An Integrated Approach 三栅极finfet的SPICE参数提取——一种集成方法

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783725

Tara Prasanna Dash, S. Das, S. Dey, E. Mohapatra, J. Jena, C. K. Maiti

引用次数: 1

Electromagnetic Bandgap Formation in Two-Dimensional Photonic Crystal Structure with DNG Materials under TE Mode TE模式下DNG材料二维光子晶体结构的电磁带隙形成

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783914

P. Chakraborty, Ratul Ghosh, Anwesha Adhikary, A. Deyasi, A. Sarkar

引用次数: 2

Surface potential based Analytical Modeling of Graded Channel Strained High-k Gate stack Dual-Material Double Gate MOSFET 基于表面电位的梯度通道应变高k栅极堆双材料双栅极MOSFET解析建模

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783284

Pritha Banerjee, Priyanka Saha, Dinesh Kumar Dash, S. Sarkar

引用次数: 1

RF/Analog & Linearity performance analysis of a downscaled JL DG MOSFET on GaAs substrate for Analog/mixed signal SOC applications 用于模拟/混合信号SOC应用的GaAs衬底上的缩小JL DG MOSFET的RF/模拟和线性性能分析

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783341

Biswajit Baral, S. Biswal, S. Swain, S. K. Das, D. Nayak, Dhananjaya Tripathy

{"title":"RF/Analog & Linearity performance analysis of a downscaled JL DG MOSFET on GaAs substrate for Analog/mixed signal SOC applications","authors":"Biswajit Baral, S. Biswal, S. Swain, S. K. Das, D. Nayak, Dhananjaya Tripathy","doi":"10.1109/DEVIC.2019.8783341","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783341","url":null,"abstract":"With time the design of RF and Analog application based circuits in MOSFET industry is changing and day by day it's becoming more and more difficult as device modeling has now entered the deep-subnanometer regime. Performance of junction less transistor is remarkable in digital application due to their ease of fabrication and superior SCEs. This paper highlights the DC, ANALOG, RF and LINEARITY performance of a Junction less Double Gate MOSFET (JL DG MOSFET) by downscaling the Channel length with the help of numerical TCAD device simulator (SILVACO). The figure of merits for DC, ANALOG, RF & LINEARITY parameters for example Transconductance $(mathrm{g}_{mathrm{m}})$, Gain transconductance frequency product (GTFP), output resistance $(mathrm{R}_{mathrm{o}mathrm{u}mathrm{t}})$, cut-off frequency $(mathrm{f}_{mathrm{T}})$, Gain bandwidth product (GBW), Transconductance generation factor $(mathrm{g}_{mathrm{m}}/mathrm{I}_{mathrm{d}})$, maximum frequency $(mathrm{f}_{max})$, Intermodulation distortion (IMD), variable intercept point (VIP) are studied and impact of downscaling in gate length have been recorded. The results conclude that down scaled junction less DG MOSFET show a great pledge to turn out to be a feasible competitor for use in SOC application.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"40 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121442913","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 0

Performance Analysis of FinFET device Using Qualitative Approach for Low-Power applications 基于定性方法的低功耗FinFET器件性能分析

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783754

Shekhar Verma, S. Tripathi, Mohinder Bassi

{"title":"Performance Analysis of FinFET device Using Qualitative Approach for Low-Power applications","authors":"Shekhar Verma, S. Tripathi, Mohinder Bassi","doi":"10.1109/DEVIC.2019.8783754","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783754","url":null,"abstract":"The introduction of Field Effect Transistor (FinFET) Technology played a leading contender in today microelectronics. FinFET structure allows to scale the device at sub-nanometer. Short channel effects can be suppressed by formation of ultra-thin fin in FinFET device. In this paper we compared the performance of the 20nm FinFET device by using different dielectric materials. We have considered only n-channel FinFET device. Simulation carried on the electron mobility, potential distribution, energy band of hole and electron, on-off current ratio (Ion/Ioff) and power dissipation of device with respect to the applied gate voltage. Mobility enhancement and higher current ratio (Ion/Ioff) is observed in proposed FinFET device having high k-dielectric material at lower voltage. This designed can be useful for low power applications due to low power dissipation. In high k-dielectric material, 1.41% improvement is observed in potential voltage with respect to low k- dielectric material when $mathbf{V}_{mathbf{gs}}$ at low voltage and 0.98% improvement is observed when $mathbf{V}_{mathbf{gs}}$ at high voltage. In high k- dielectric material 15% hike is observed in the energy conduction band as compared to low k-dielectric material when $mathbf{V}_{mathbf{gs}}$ at low voltage and 14% hike is observed when $mathbf{v}_{mathbf{gs}}$ at high voltage.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"25 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123296096","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}

引用次数: 18

Analytical Modeling and Simulation of Low Power Salient Source Double Gate TFET 低功率凸源双栅极TFET的解析建模与仿真

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783677

Bijoy Goswami, Debadipta Basak, A. Bhattacharya, Koelgeet Kaur, Sutanni Bhowmick, S. Sarkar

引用次数: 1

Improvement of the Gain Accuracy of the Instrumentation Amplifier Using a Very High Gain Operational Amplifier 用高增益运算放大器提高仪表放大器的增益精度

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783414

Maitraiyee Konar, R. Sahu, S. Kundu

引用次数: 14

Adaptive Jaya Optimization Technique for Economic Load Dispatch Considering Valve Point Effect 考虑阀点效应的经济负荷调度自适应Jaya优化技术

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783691

S. Basak, Swaraj Banerjee

引用次数: 3

Message from General Chair & Editor 总主席兼编辑的信息

2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/devic.2019.8783299

引用次数: 0