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Synthesis of Morphological-Variant ZnO nanostructures 形貌变化ZnO纳米结构的合成
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783324
A. Dikshit, Kamal, A. Singh, J. Rana, R. Singh, Nillohit Mukhrjee, P. Chakrabarti
{"title":"Synthesis of Morphological-Variant ZnO nanostructures","authors":"A. Dikshit, Kamal, A. Singh, J. Rana, R. Singh, Nillohit Mukhrjee, P. Chakrabarti","doi":"10.1109/DEVIC.2019.8783324","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783324","url":null,"abstract":"Nanostructures of zinc oxide have great potential in optoelectronics as well as in sensing applications. Here, we report the controlled and systematic growth of ZnO nanostructure by hydrothermal and vapor-liquid-solid (VLS) techniques, which can be used in various electronics and optoelectronic devices. The effect of various growth parameters (growth temperature, annealing time, the thickness of seed layer, to name a few) on the morphology of ZnO nanostructures has been studied. Ultra-long nanowires of length more than $300mumathrm{m}$ have been synthesized with aspect ratio around 10.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"49 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"125610268","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Comparative Analysis of Underlapped Silicon on Insulator and Underlapped Silicon on Nothing Dielectric and Charge Modulated FET based Biosensors 基于介电和电荷调制场效应晶体管的生物传感器的绝缘体上和无介电和电荷调制层间硅的比较分析
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783714
Khuraijam Nelson Singh, P. Dutta
{"title":"Comparative Analysis of Underlapped Silicon on Insulator and Underlapped Silicon on Nothing Dielectric and Charge Modulated FET based Biosensors","authors":"Khuraijam Nelson Singh, P. Dutta","doi":"10.1109/DEVIC.2019.8783714","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783714","url":null,"abstract":"A biosensor based on silicon on insulator (SOI) MOSFET provides many advantages over the conventional biosensors but still suffers from the inherent problem which exists in SOI structures. Silicon on nothing (SON) MOSFET which is a derivative of SOI MOSFET is an option which has been considered by many as an alternative due to its excellent performances. In this study, underlapped silicon on insulator (USOI) and underlapped silicon on nothing (USON) dielectric and charge modulated FET (DCMFET) has been compared for biosensing application. Modulation of the devices electrical characteristics, namely surface potential, threshold voltage, and sensitivity have been studied to understand the sensing of biomolecules without labeling. Detection of biomolecules is evaluated as a shift of threshold voltage of the devices with the change in biomolecules dielectric constants and charges. The data obtained from the analytical models showed both the devices as highly sensitive; however, USON-DCMFET is found to be the better choice. The analytical models have also been verified by using the data obtained from the 2-D numerical simulations performed using SILVACO ATLAS.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"133652167","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 4
Optimization of Electrical Parameters for the Gate Stack Double Gate (GSDG) MOSFET using Simplex-PSO Algorithm 基于Simplex-PSO算法的栅极堆叠双栅极MOSFET电参数优化
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783730
Dibyendu Chowdhury, B. P. De, K. B. Maji, Sumalya Ghosh, R. Kar, D. Mandal
{"title":"Optimization of Electrical Parameters for the Gate Stack Double Gate (GSDG) MOSFET using Simplex-PSO Algorithm","authors":"Dibyendu Chowdhury, B. P. De, K. B. Maji, Sumalya Ghosh, R. Kar, D. Mandal","doi":"10.1109/DEVIC.2019.8783730","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783730","url":null,"abstract":"In this article, the electrical parameters of the Gate Stack Double Gate (GSDG) MOSFET are optimized utilizing the Simplex-Particle Swarm Optimization (Simplex-PSO) algorithm. The electrical parameters like the OFF-state current, transconductance and subthreshold swing have been considered to formulate the overall Cost Function (CF). The overall CF is achieved by the weighted sum approach method. The results attained from the Simplex-PSO are formed to be better than the previous literature.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"123953630","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 3
Performance Prediction of Stacked Nanowire Transistors in the Presence of Random Discrete Dopants and Metal Gate Granularity 随机掺杂和金属栅粒度下堆叠纳米线晶体管的性能预测
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783687
S. Dey, E. Mohapatra, J. Jena, S. Das, Tara Prasanna Dash, C. K. Maiti
{"title":"Performance Prediction of Stacked Nanowire Transistors in the Presence of Random Discrete Dopants and Metal Gate Granularity","authors":"S. Dey, E. Mohapatra, J. Jena, S. Das, Tara Prasanna Dash, C. K. Maiti","doi":"10.1109/DEVIC.2019.8783687","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783687","url":null,"abstract":"Gate-all-around nanowire field effect transistors (GAA-NW-FETs) in a horizontal configuration is now being considered as a strong candidate to extend today's CMOS technology to its ultimate scaling limits. In this paper, full 3-D device simulations are performed to study the effect of random discrete dopants (RDD) and metal gate granularity (MGG) on the performance of a 10nm channel length vertically stacked silicon nanowire FETs. The impact of metal grain crystallographic orientation on the gate work function and presence of discrete dopants on transistor threshold voltage is reported. The discrete dopants have been distributed randomly in the source/drain and channel regions of the device. Due to the small dimensions of the transistor a quantum transport formalism has been deployed in simulation. Our results show the magnitude and importance of RDD and MGG and the need for process optimization to minimize device parameter variations in sub-10nm technology nodes.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"63 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116028106","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Effect of High-K Spacer on the Performance of Gate-Stack Uniformly doped DG-MOSFET 高k间隔层对栅极堆叠均匀掺杂DG-MOSFET性能的影响
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783272
S. K. Das, S. Swain, S. Biswal, D. Nayak, U. Nanda, Biswajit Baral, Dhananjaya Tripathy
{"title":"Effect of High-K Spacer on the Performance of Gate-Stack Uniformly doped DG-MOSFET","authors":"S. K. Das, S. Swain, S. Biswal, D. Nayak, U. Nanda, Biswajit Baral, Dhananjaya Tripathy","doi":"10.1109/DEVIC.2019.8783272","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783272","url":null,"abstract":"In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect to different spacer variations in order to reduce the short channel effect challenges and simultaneously increasing the device performance. Silicon is used as the channel material along with the gate stacked technology for studying the analog performance and Radio Frequency (RF) performance of the device. For gate stacking, two types of oxides are used- one denoting low-K i.e SiO2 and the other as high-K i.e- HfO2. Spacers with various permittivities were used to understand their effects on the performance of the device. The simulation result shows that the use of spacer material affected both the analog and RF behavior of the device significantly. The computer aided design (TCAD) simulations have been carried by SILVACO International.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"21 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"131386669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 8
Novel Self-Pipelining Strategy for Efficient Multiplication 一种高效乘法的自流水线策略
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783651
Rahul Pal, J. Ghosh, A. Saha
{"title":"Novel Self-Pipelining Strategy for Efficient Multiplication","authors":"Rahul Pal, J. Ghosh, A. Saha","doi":"10.1109/DEVIC.2019.8783651","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783651","url":null,"abstract":"In this work a novel self-pipelining strategy with proper synchronization among subsequent stages for low-power high-speed digital multiplication is explored. The true and complementary clock inputs are alternatively applied to each subsequent self-latching stage to achieve proposed self-pipelining operation. A $mathbf{4}-mathbf{b}times mathbf{4}-mathbf{b}$ self-pipelined Wallace-tree multiplier based on aforesaid idea has been designed first. Next, the $mathbf{4}-mathbf{b}times mathbf{4}-mathbf{b}$ multiplier thus designed has been exploited in order to design proposed self-pipelined $mathbf{8}-mathbf{b} times mathbf{8}-mathbf{b}$ multiplier with decomposition logic. All the designs and optimization are performed on TSMC $mathbf{0.18}mathbf{mu} mathbf{m}$ CMOS technology based on BSIM3 device parameters with 1.8V supply rail and at 25°C temperature using S-Edit of Tanner EDA V.13. The performance of designed multiplier has been evaluated with T-Spice simulation using W-Edit. A benchmarking comparison with respect to latest competitive design establishes superiority of proposed idea.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"121841318","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
Smart Power Theft Detection System 智能电力盗窃检测系统
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783395
Nitin K Mucheli, U. Nanda, D. Nayak, P. Rout, S. Swain, S. K Das, S. Biswal
{"title":"Smart Power Theft Detection System","authors":"Nitin K Mucheli, U. Nanda, D. Nayak, P. Rout, S. Swain, S. K Das, S. Biswal","doi":"10.1109/DEVIC.2019.8783395","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783395","url":null,"abstract":"Power theft is normally done by two methods that is bypassing or hooking. So to detect it, a system (current measuring and comparing) is proposed in which the household distribution of current is done indirectly from the electric pole to an intermediate distributor box and then to the individual houses. The current is measured periodically in the distributor box and is posted to the server database for each house using GSM/GPRS module. Similarly, for each house electric meter is designed which can measure the value of the current and post the same to the server database periodically using GSM/GPRS module. At the time of the installation of the electric meter the details of the users are stored in the database through a user friendly mobile application including the address, latitude, longitude using mobile GPS and the photograph of the user's house/area. Upon successful comparison between the current values from distributor box and electric meter in the server if we get a marginal difference between the currents then the theft is detected. Finally, the details of the user are shared with the authorized mobile application including the address and photograph of the area. The latitude and longitude are also used to show the area of theft in Google maps. And hence the required steps are taken. The same process is used for hooking but on the individual electric poles.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"48 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127239142","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 10
Mobility Modulation in V-shaped Double Quantum Well based HEMT Structure 基于v型双量子阱的HEMT结构的迁移率调制
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783242
S. Palo, A. K. Panda, T. Sahu, N. Sahoo, T. C. Tripathy
{"title":"Mobility Modulation in V-shaped Double Quantum Well based HEMT Structure","authors":"S. Palo, A. K. Panda, T. Sahu, N. Sahoo, T. C. Tripathy","doi":"10.1109/DEVIC.2019.8783242","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783242","url":null,"abstract":"In the present work, modulation of low temperature mobility $mathbf{mu}$ is studied theoretically with the application of electric field $pmb{F}_{pmb{e}}$ in a double quantum well HEMT structure whose channel is craved from $pmb{Al}_{x}pmb{Ga}_{mathit{1}-x}pmb{As}$ having V-shaped potential. We show that there is an unusual rise in $pmb{mu}$ at the transition field where the change in subband occupancy occurs, unlike that of the conventional square quantum well systems.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"12 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"127897373","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 0
Performance analysis of optical logic XOR gate using dual-control Tera Hertz Optical Asymmetric Demultiplexer (DCTOAD) 双控Tera赫兹光不对称解复用器光逻辑异或门性能分析
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783496
K. Maji, K. Mukherjee
{"title":"Performance analysis of optical logic XOR gate using dual-control Tera Hertz Optical Asymmetric Demultiplexer (DCTOAD)","authors":"K. Maji, K. Mukherjee","doi":"10.1109/DEVIC.2019.8783496","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783496","url":null,"abstract":"In this paper we have proposed performance of optical logic XOR gate using dual control Tera Hertz Optical Asymmetric Demultiplexer (DCTOAD). For the first time DCTOAD based XOR gate with soliton pulse is proposed and analyzed in terms of eye diagram and quality factor. Extinction Ratio (ER), Contrast Ratio(CR) and relative eye opening are also calculated. High Q factor implies bit error free operation.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"6 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"116829669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 7
Up-state and Down-state Capacitance Measurement in RF MEMS One-bit Switch Designed at Microwave Frequency Range 微波频率下射频MEMS位开关上、下电容测量
2019 Devices for Integrated Circuit (DevIC) Pub Date : 2019-03-01 DOI: 10.1109/DEVIC.2019.8783948
P. Debnath, A. Deyasi, A. Sarkar
{"title":"Up-state and Down-state Capacitance Measurement in RF MEMS One-bit Switch Designed at Microwave Frequency Range","authors":"P. Debnath, A. Deyasi, A. Sarkar","doi":"10.1109/DEVIC.2019.8783948","DOIUrl":"https://doi.org/10.1109/DEVIC.2019.8783948","url":null,"abstract":"Insertion loss, isolation factor and return loss of one-bit RF MEMS switch designed at higher microwave frequency ranges is numerically measured for computation of up-state and down-state capacitance. SiO2 is the material considered for design purpose and simulation is performed over the entire microwave frequency range in order to investigate the position of maximum loss (peak point). Overlap cross-sectional area is varied over the possible fabrication range, and losses are measured for both actuated as well as unactuated states of the device over the varying overlap region. Both up and down state capacitances are measured which are higher with increase of active area. Return loss of −50 dB is observed for unactuated state whereas it becomes very low (~ −7.5 dB) for actuated device. Also for down state capacitance measurement, isolation increases upto −40 dB. Results are very useful for phase-shifter design at microwave spectrum.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"79 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"117084683","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
引用次数: 1
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