高k间隔层对栅极堆叠均匀掺杂DG-MOSFET性能的影响

S. K. Das, S. Swain, S. Biswal, D. Nayak, U. Nanda, Biswajit Baral, Dhananjaya Tripathy
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引用次数: 8

摘要

在这项工作中,我们分析了栅极堆叠双栅(DG) MOSFET在不同间隔变化方面的新颖性,以减少短通道效应挑战,同时提高器件性能。采用硅作为通道材料,结合栅极堆叠技术研究器件的模拟性能和射频(RF)性能。对于栅极堆积,使用两种类型的氧化物-一种表示低k,即SiO2,另一种表示高k,即HfO2。使用不同介电常数的间隔片来了解它们对器件性能的影响。仿真结果表明,间隔材料的使用对器件的模拟性能和射频性能都有显著影响。计算机辅助设计(TCAD)仿真由SILVACO国际公司进行。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
Effect of High-K Spacer on the Performance of Gate-Stack Uniformly doped DG-MOSFET
In this work, we have analyzed the novelty of the Gate Stack Double Gate (DG) MOSFET with respect to different spacer variations in order to reduce the short channel effect challenges and simultaneously increasing the device performance. Silicon is used as the channel material along with the gate stacked technology for studying the analog performance and Radio Frequency (RF) performance of the device. For gate stacking, two types of oxides are used- one denoting low-K i.e SiO2 and the other as high-K i.e- HfO2. Spacers with various permittivities were used to understand their effects on the performance of the device. The simulation result shows that the use of spacer material affected both the analog and RF behavior of the device significantly. The computer aided design (TCAD) simulations have been carried by SILVACO International.
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