Novel Self-Pipelining Strategy for Efficient Multiplication

Abstract

In this work a novel self-pipelining strategy with proper synchronization among subsequent stages for low-power high-speed digital multiplication is explored. The true and complementary clock inputs are alternatively applied to each subsequent self-latching stage to achieve proposed self-pipelining operation. A $\mathbf{4}-\mathbf{b}\times \mathbf{4}-\mathbf{b}$ self-pipelined Wallace-tree multiplier based on aforesaid idea has been designed first. Next, the $\mathbf{4}-\mathbf{b}\times \mathbf{4}-\mathbf{b}$ multiplier thus designed has been exploited in order to design proposed self-pipelined $\mathbf{8}-\mathbf{b}\ \times\ \mathbf{8}-\mathbf{b}$ multiplier with decomposition logic. All the designs and optimization are performed on TSMC $\mathbf{0.18}\mathbf{\mu} \mathbf{m}$ CMOS technology based on BSIM3 device parameters with 1.8V supply rail and at 25°C temperature using S-Edit of Tanner EDA V.13. The performance of designed multiplier has been evaluated with T-Spice simulation using W-Edit. A benchmarking comparison with respect to latest competitive design establishes superiority of proposed idea.