{"title":"A Low Power Hardware Implementation of Lifting based Reversible Watermarking for Medical Image","authors":"Poulami Jana, G. Maity, Himadri S. Mandal","doi":"10.1109/DEVIC.2019.8783370","DOIUrl":null,"url":null,"abstract":"A lifting domain reversible data hiding is presented here. A content based watermark is produced from selective $(4\\times 4)$ sized coefficient blocks of particular sub-band. One covert key is utilized to secure the watermark for access management which is specified by user. The secure watermark is implanted within same coefficient block $(4\\times 4)$. In receiver side the retrieval of original image is done by the authentic user's secure key. For real time application the ‘very large scale integration’ (VLSI) architecture of this proposed encoder is designed in hardware. Simulation of the encoder is done by ‘field programmable gate array’ (FPGA) kit. The experimentation is performed over a range of benchmark images. The results justify the supremacy of the method. The encoder module consumes only 59.20mW power when operated at 120.135MHz frequency in case of real time implementation.","PeriodicalId":294095,"journal":{"name":"2019 Devices for Integrated Circuit (DevIC)","volume":"106 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2019-03-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2019 Devices for Integrated Circuit (DevIC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DEVIC.2019.8783370","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
A lifting domain reversible data hiding is presented here. A content based watermark is produced from selective $(4\times 4)$ sized coefficient blocks of particular sub-band. One covert key is utilized to secure the watermark for access management which is specified by user. The secure watermark is implanted within same coefficient block $(4\times 4)$. In receiver side the retrieval of original image is done by the authentic user's secure key. For real time application the ‘very large scale integration’ (VLSI) architecture of this proposed encoder is designed in hardware. Simulation of the encoder is done by ‘field programmable gate array’ (FPGA) kit. The experimentation is performed over a range of benchmark images. The results justify the supremacy of the method. The encoder module consumes only 59.20mW power when operated at 120.135MHz frequency in case of real time implementation.